74ACT11074DB

更新时间： 2024-11-30 22:22:07

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
5页	84K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74ACT11074DB 数据手册

74ACT11074

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH CLEAR AND PRESET

SCAS498A – DECEMBER 1986 – REVISED APRIL 1996

D, DB, OR N PACKAGE

(TOP VIEW)

Inputs Are TTL-Voltage Compatible

Center-Pin V and GND Configurations to

Minimize High-Speed Switching Noise

1PRE

14 1CLK

EPIC (Enhanced-Performance Implanted

CMOS) 1- m Process

1CLR

500-mA Typical Latch-Up Immunity

at 125°C

GND

2CLR

Package Options Include Plastic

Small-Outline (D) and Shrink Small-Outline

(DB) Packages, and Standard Plastic

300-mil DIPs (N)

2PRE

2CLK

description

This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE)

or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR

are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs

on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly

related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed

without affecting the levels at the outputs.

The 74ACT11074 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OUTPUTS

PRE

CLK

CLR

↑

†

This configuration is unstable; that is, it does not

persist when either PRE or CLR returns to its

inactive (high) level.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5

中文翻译

下载PDF

与74ACT11074DB相关器件

型号	品牌	获取价格	描述	数据表
74ACT11074DBLE	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
74ACT11074DBR	TI	获取价格	Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SSOP -40 to 85
74ACT11074DG4	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
74ACT11074DR	ETC	获取价格	Dual D-Type Flip-Flop
74ACT11074DRE4	TI	获取价格	ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTI
74ACT11074DRG4	TI	获取价格	ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, PLASTI
74ACT11074D-T	PHILIPS	获取价格	D Flip-Flop, 2-Func, Positive Edge Triggered, CMOS, PDSO14
74ACT11074D-T	YAGEO	获取价格	D Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMO
74ACT11074N	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
74ACT11074N	PHILIPS	获取价格	D Flip-Flop, 2-Func, Positive Edge Triggered, CMOS, PDIP14,

与74ACT11074DB相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

53
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

42
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

70
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

66

产品中心

服务支持

精选活动

关于我们

帮助中心

74ACT11074DB

74ACT11074DB 数据手册

与74ACT11074DB相关器件

与74ACT11074DB相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

74ACT11074DB

74ACT11074DB 数据手册

与74ACT11074DB相关器件

与74ACT11074DB相关文章

您还可以找

您在本页遇到什么问题？