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74ACT11074DBLE PDF预览

74ACT11074DBLE

更新时间: 2024-12-02 01:12:03
品牌 Logo 应用领域
德州仪器 - TI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
5页 84K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

74ACT11074DBLE 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP14,.3针数:14
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.68系列:ACT
JESD-30 代码:R-PDSO-G14长度:6.2 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:100000000 Hz最大I(ol):0.024 A
位数:1功能数量:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
传播延迟(tpd):8.8 ns认证状态:Not Qualified
座面最大高度:2 mm子类别:FF/Latches
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:5.3 mm
最小 fmax:100 MHz

74ACT11074DBLE 数据手册

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74ACT11074  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
SCAS498A – DECEMBER 1986 – REVISED APRIL 1996  
D, DB, OR N PACKAGE  
(TOP VIEW)  
Inputs Are TTL-Voltage Compatible  
Center-Pin V and GND Configurations to  
Minimize High-Speed Switching Noise  
CC  
1PRE  
1Q  
1
2
3
4
5
6
7
14 1CLK  
EPIC (Enhanced-Performance Implanted  
CMOS) 1- m Process  
13  
12  
11  
10  
9
1D  
1Q  
1CLR  
500-mA Typical Latch-Up Immunity  
at 125°C  
GND  
2Q  
V
CC  
2CLR  
2D  
Package Options Include Plastic  
Small-Outline (D) and Shrink Small-Outline  
(DB) Packages, and Standard Plastic  
300-mil DIPs (N)  
2Q  
8
2PRE  
2CLK  
description  
This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE)  
or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR  
are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs  
on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly  
related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed  
without affecting the levels at the outputs.  
The 74ACT11074 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLK  
D
X
X
X
H
L
Q
H
L
Q
L
CLR  
H
X
X
X
H
L
H
L
L
H
H
H
H
H
L
L
H
H
H
H
H
L
X
Q
Q
0
0
This configuration is unstable; that is, it does not  
persist when either PRE or CLR returns to its  
inactive (high) level.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

74ACT11074DBLE 替代型号

型号 品牌 替代类型 描述 数据表
74ACT11074NSR TI

完全替代

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
74ACT11074DBR TI

完全替代

Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset 14-SSOP -40 to 85
74ACT11074N TI

完全替代

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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74ACT11074DG4 TI

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74ACT11074DR ETC

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74ACT11074DRE4 TI

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74ACT11074DRG4 TI

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74ACT11074D-T PHILIPS

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D Flip-Flop, 2-Func, Positive Edge Triggered, CMOS, PDSO14
74ACT11074D-T YAGEO

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D Flip-Flop, ACT Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, CMO
74ACT11074N TI

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DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
74ACT11074N PHILIPS

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D Flip-Flop, 2-Func, Positive Edge Triggered, CMOS, PDIP14,
74ACT11074NE4 TI

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ACT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14, 0.300