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74AC11238N PDF预览

74AC11238N

更新时间: 2024-11-07 21:13:23
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
9页 112K
描述
3-Line To 8-Line Decoders/Demultiplexers 16-PDIP -40 to 85

74AC11238N 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:20
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.74
其他特性:3 ENABLE INPUTS; CENTER VCC/GND PINS系列:AC
JESD-30 代码:R-PDIP-T16长度:19.305 mm
负载电容(CL):50 pF逻辑集成电路类型:OTHER DECODER/DRIVER
最大I(ol):0.024 A功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3/5 VProp。Delay @ Nom-Sup:11 ns
传播延迟(tpd):10.2 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

74AC11238N 数据手册

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54AC11238, 74AC11238  
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS  
SCAS039A – APRIL 1988 – REVISED APRIL 1993  
54AC11238 . . . J PACKAGE  
74AC11238 . . . D OR N PACKAGE  
Designed Specifically for High-Speed  
Memory Decoders and Data Transmission  
Systems  
(TOP VIEW)  
Noninverting Version of AC11138  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
Y0  
A
Y1  
Y2  
Incorporates 3 Enable Inputs to Simplify  
Cascading and/or Data Reception  
B
Y3  
Flow-Through Architecture Optimizes  
C
V
GND  
Y4  
PCB Layout  
CC  
Center-Pin V  
and GND Configurations  
Minimize High-Speed Switching Noise  
G1  
Y5  
CC  
G2A  
G2B  
Y6  
Y7  
EPIC (Enhanced-Performance Implanted  
CMOS) 1- m Process  
500-mA Typical Latch-Up Immunity  
at 125°C  
54AC11238 . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
3
2
1
20 19  
18  
A
Y0  
NC  
Y1  
Y2  
G2A  
17 G2B  
4
5
6
7
8
description  
16  
15  
14  
NC  
Y7  
Y6  
The AC11238 circuit is designed to be  
used in high-performance memory-decoding or  
data-routing applications requiring very short  
propagation delay times. In high-performance  
memory systems, this decoder can be used to  
minimize the effects of system decoding. When  
employed with high-speed memories utilizing a  
fast enable circuit, the delay times of this decoder  
9 10 11 12 13  
NC – No internal connection  
and the enable time of the memory are usually less than the typical access time of the memory. This means that  
the effective system delay introduced by the decoder is negligible.  
The conditions at the binary select inputs and the three enable inputs select one of eight input lines. Two  
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.  
A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one  
inverter. An enable input can be used as a data input for demultiplexing applications.  
The 54AC11238 is characterized for operation over the full military temperature range of – 55°C to 125°C. The  
74AC11238 is characterized for operation from – 40°C to 85°C.  
EPIC is a trademark of Texas Instruments Incorporated.  
PRODUCTION DATA information is current as of publication date.  
Copyright 1993, Texas Instruments Incorporated  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily  
include testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

74AC11238N 替代型号

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CD74AC139EE4 TI

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DUAL 2-LINE TO 4-LINE DECODER/DEMULTIPLEXER