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74AC11240PWG4 PDF预览

74AC11240PWG4

更新时间: 2024-11-07 20:40:47
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
14页 470K
描述
Octal Buffers/Drivers 24-TSSOP -40 to 85

74AC11240PWG4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP24,.25针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.6控制类型:ENABLE LOW
系列:ACJESD-30 代码:R-PDSO-G24
JESD-609代码:e4长度:7.8 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:4功能数量:2
端口数量:2端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP24,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TUBE
峰值回流温度(摄氏度):260电源:3.3/5 V
Prop。Delay @ Nom-Sup:8.4 ns传播延迟(tpd):11.7 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

74AC11240PWG4 数据手册

 浏览型号74AC11240PWG4的Datasheet PDF文件第2页浏览型号74AC11240PWG4的Datasheet PDF文件第3页浏览型号74AC11240PWG4的Datasheet PDF文件第4页浏览型号74AC11240PWG4的Datasheet PDF文件第5页浏览型号74AC11240PWG4的Datasheet PDF文件第6页浏览型号74AC11240PWG4的Datasheet PDF文件第7页 
74AC11240  
OCTAL BUFFER/LINE DRIVER  
WITH 3-STATE OUTPUTS  
SCAS448A – MAY 1987 – REVISED APRIL 1996  
DB, DW, OR NT PACKAGE  
(TOP VIEW)  
Flow-Through Architecture Optimizes  
PCB Layout  
Center-Pin V  
Minimize High-Speed Switching Noise  
and GND Configurations  
CC  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
1Y1  
1Y2  
1Y3  
1OE  
1A1  
1A2  
1A3  
1A4  
2
EPIC (Enhanced-Performance Implanted  
CMOS) 1- m Process  
3
4
1Y4  
500-mA Typical Latch-Up Immunity at  
125°C  
5
GND  
GND  
GND  
GND  
2Y1  
2Y2  
2Y3  
2Y4  
6
V
V
CC  
CC  
7
Package Options Include Plastic  
Small-Outline (DW) and Shrink  
Small-Outline (DB) Packages, and Standard  
Plastic 300-mil DIPs (NT)  
8
2A1  
2A2  
2A3  
2A4  
2OE  
9
10  
11  
12  
description  
Thisoctalbuffer/linedriverisdesignedspecifically  
to improve both the performance and density of  
3-state memory address drivers, clock drivers,  
and bus-oriented receivers and transmitters. This  
device  
provides  
inverting  
outputs  
and  
symmetrical active-low output-enable (OE)  
inputs. This device features high fan-out and  
improved fan-in.  
The 74AC11240 is organized as two 4-bit buffers/line drivers with separate OE inputs. When OE is low, the  
device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the  
high-impedance state.  
The 74AC11240 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
L
A
H
L
L
L
H
Z
H
X
logic symbol  
24  
13  
1OE  
EN  
2OE  
EN  
23  
1A1  
22  
1
2
3
4
17  
16  
15  
14  
9
10  
11  
12  
1
1
1Y1  
2Y1  
2Y2  
2Y3  
2Y4  
2A1  
2A2  
2A3  
2A4  
1Y2  
1Y3  
1Y4  
1A2  
21  
1A3  
20  
1A4  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

74AC11240PWG4 替代型号

型号 品牌 替代类型 描述 数据表
74AC11240PWE4 TI

类似代替

Octal Buffers/Drivers 24-TSSOP -40 to 85

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