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74ABT648PW,118 PDF预览

74ABT648PW,118

更新时间： 2024-11-17 14:46:59
品牌 Logo 应用领域
恩智浦 - NXP 输入元件信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
19页 105K
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74ABT648PW

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74ABT648PW,118 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：4.40 MM, PLASTIC, SOT-355-1, TSSOP-24
针数：24Reach Compliance Code：unknown
风险等级：5.79其他特性：DIRECTION CONTROL; SELECT INPUT FOR MULTIPLEXED TRANSMISSION OF REGISTERED OR REAL TIME DATA
系列：ABTJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：7.8 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260传播延迟（tpd）：6.1 ns
认证状态：Not Qualified座面最大高度：1.1 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40宽度：4.4 mm
Base Number Matches：1

74ABT648PW,118 数据手册

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74ABT648  
Octal transceiver/register; inverting; 3-state  
Rev. 04 — 27 April 2005  
Product data sheet  
1. General description  
The 74ABT648 high-performance BiCMOS device combines low static and dynamic  
power dissipation with high speed and high output drive.  
The 74ABT648 transceiver/register consists of bus transceiver circuits with inverting  
3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed  
transmission of data directly from the input bus or the internal registers. Data on the A or B  
bus will be clocked into the registers as the appropriate clock pin goes HIGH.  
Output enable (OE) and direction (DIR) pins are provided to control the transceiver  
function.  
In the transceiver mode, data present at the high-impedance port may be stored in either  
the A or B register or both.  
The select (SAB, SBA) pins determine whether data is stored or transferred through the  
device in real time. The DIR determines which bus will receive data when the OE is active  
(LOW).  
In the isolation mode (OE = HIGH), data from bus A may be stored in the B register and/or  
data from bus B may be stored in the A register. Outputs from real time or stored registers  
will be inverted. When an output function is disabled, the input function is still enabled and  
may be used to store and transmit data. Only one of the two buses A or B may be driven  
at a time.  
2. Features  
■ Combines 74ABT245 and 74ABT374A type functions in one device  
■ Independent registers for A and B buses  
■ Multiplexed real time and stored data  
■ 3-state buffers  
■ Live insertion and extraction permitted  
■ Output capability: +64 mA and −32 mA  
■ Power-up 3-state  
■ Power-up reset  
■ Latch-up protection:  
◆ JESD78: exceeds 500 mA  
■ ESD protection:  
◆ MIL STD 883 method 3015: exceeds 2000 V  
◆ Machine model: exceeds 200 V  
 
 
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