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74ABT652A PDF预览

74ABT652A

更新时间: 2024-11-16 22:56:15
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
8页 123K
描述
Octal transceiver/register, non-inverting 3-State

74ABT652A 数据手册

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Philips Semiconductors  
Product specification  
Octal transceiver/register, non-inverting (3-State)  
74ABT652A  
FEATURES  
Independent registers for A and B buses  
DESCRIPTION  
The 74ABT652A high-performance BiCMOS device combines low  
static and dynamic power dissipation with high speed and high  
output drive.  
Multiplexed real-time and stored data  
3-State outputs  
The 74ABT652A transceiver/register consists of bus transceiver  
circuits with 3-State outputs, D-type flip-flops, and control circuitry  
arranged for multiplexed transmission of data directly from the input  
bus or the internal registers. Data on the A or B bus will be clocked  
into the registers as the appropriate clock pin goes High. Output  
Enable (OEAB, OEBA) and Select (SAB, SBA) pins are provided for  
bus management.  
Live insertion/extraction permitted  
Power-up 3-State  
Power-up reset  
Output capability: +64mA/–32mA  
Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17  
ESD protection exceeds 2000 V per MIL STD 883 Method 3015  
and 200 V per Machine Model  
QUICK REFERENCE DATA  
CONDITIONS  
= 25°C; GND = 0V  
SYMBOL  
PARAMETER  
TYPICAL  
UNIT  
T
amb  
t
t
Propagation delay  
3.7  
4.3  
PLH  
PHL  
C = 50pF; V = 5V  
ns  
pF  
pF  
µA  
L
CC  
CPBA to An or CPAB to Bn  
Input capacitance  
C
V = 0V or V  
I CC  
4
7
IN  
Outputs disabled;  
= 0V or V  
C
I/O capacitance  
I/O  
V
O
CC  
I
Total supply current  
Outputs disabled; V =5.5V  
110  
CCZ  
CC  
ORDERING INFORMATION  
PACKAGES  
TEMPERATURE RANGE  
ORDER CODE  
74ABT652AN  
74ABT652AD  
74ABT652ADB  
DRAWING NUMBER  
SOT222-1  
24-pin plastic DIP  
–40°C to +85°C  
–40°C to +85°C  
–40°C to +85°C  
24-pin plastic SOL  
SOT137-1  
24-pin plastic SSOP Type II  
SOT340-1  
24-pin plastic TSSOP Type I  
–40°C to +85°C  
74ABT652APW  
SOT355-1  
PIN CONFIGURATION  
PIN DESCRIPTION  
PIN NUMBER SYMBOL  
FUNCTION  
CPAB /  
CPBA  
CPAB  
SAB  
OEAB  
A0  
1
2
3
4
5
6
7
8
9
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
V
CC  
1, 23  
A to B clock input / B to A clock input  
CPBA  
SBA  
OEBA  
B0  
SAB /  
A to B select input / B to A select  
input  
2, 22  
SBA  
A to B Output Enable input /  
B to A Output Enable input  
(active–Low)  
OEAB /  
OEBA  
3, 21  
A1  
A2  
B1  
4, 5, 6, 7,  
8, 9, 10, 11  
A0 – A7 Data inputs/outputs (A side)  
B0 – B7 Data inputs/outputs (B side)  
A3  
B2  
A4  
B3  
20, 19, 18, 17,  
16, 15, 14, 13  
A5  
B4  
12  
24  
GND  
Ground (0V)  
A6 10  
A7 11  
B5  
V
CC  
Positive supply voltage  
B6  
GND 12  
B7  
SA00094  
1
1995 Apr 19  
853-1614 15144  

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