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74LS193 PDF预览

74LS193

更新时间: 2024-01-18 04:06:47
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 计数器
页数 文件大小 规格书
9页 278K
描述
PRESETTABLE BCD/DECADE UP/DOWN COUNTER PRESETTABLE 4-BIT BINARY UP/DOWN COUNTER

74LS193 技术参数

生命周期:Contact ManufacturerReach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.77
Is Samacsys:N逻辑集成电路类型:BINARY COUNTER
Base Number Matches:1

74LS193 数据手册

 浏览型号74LS193的Datasheet PDF文件第2页浏览型号74LS193的Datasheet PDF文件第3页浏览型号74LS193的Datasheet PDF文件第4页浏览型号74LS193的Datasheet PDF文件第5页浏览型号74LS193的Datasheet PDF文件第6页浏览型号74LS193的Datasheet PDF文件第7页 
SN54/74LS192  
SN54/74LS193  
PRESETTABLE BCD/DECADE  
UP/DOWN COUNTER  
PRESETTABLE 4-BIT BINARY  
UP/DOWN COUNTER  
PRESETTABLE BCD/DECADE  
UP/DOWN COUNTER  
PRESETTABLE 4-BIT BINARY  
UP/DOWN COUNTER  
The SN54/74LS192 is an UP/DOWN BCD Decade (8421) Counter and the  
SN54/74LS193 is an UP/DOWN MODULO-16 Binary Counter. Separate  
Count Up and Count Down Clocks are used and in either counting mode the  
circuits operate synchronously. The outputs change state synchronous with  
the LOW-to-HIGH transitions on the clock inputs.  
LOW POWER SCHOTTKY  
Separate Terminal Count Up and Terminal Count Down outputs are  
provided which are used as the clocks for a subsequent stages without extra  
logic, thus simplifying multistage counter designs. Individual preset inputs  
allow the circuits to be used as programmable counters. Both the Parallel  
Load (PL) and the Master Reset (MR) inputs asynchronously override the  
clocks.  
J SUFFIX  
CERAMIC  
CASE 620-09  
16  
1
Low Power . . . 95 mW Typical Dissipation  
High Speed . . . 40 MHz Typical Count Frequency  
Synchronous Counting  
Asynchronous Master Reset and Parallel Load  
Individual Preset Inputs  
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
1
Cascading Circuitry Internally Provided  
Input Clamp Diodes Limit High Speed Termination Effects  
D SUFFIX  
SOIC  
CASE 751B-03  
CONNECTION DIAGRAM DIP (TOP VIEW)  
16  
1
ORDERING INFORMATION  
NOTE:  
SN54LSXXXJ  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
Ceramic  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
LOGIC SYMBOL  
PIN NAMES  
LOADING (Note a)  
HIGH  
LOW  
CP  
CP  
MR  
PL  
Count Up Clock Pulse Input  
Count Down Clock Pulse Input  
Asynchronous Master Reset (Clear) Input  
Asynchronous Parallel Load (Active LOW) Input  
Parallel Data Inputs  
Flip-Flop Outputs (Note b)  
Terminal Count Down (Borrow) Output (Note b)  
Terminal Count Up (Carry) Output (Note b)  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
10 U.L. 5 (2.5) U.L.  
10 U.L. 5 (2.5) U.L.  
10 U.L. 5 (2.5) U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
U
D
P
Q
TC  
TC  
n
n
D
U
NOTES:  
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
b. Temperature Ranges.  
FAST AND LS TTL DATA  
5-351  

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