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72V85L20PAI PDF预览

72V85L20PAI

更新时间： 2024-11-16 20:53:39
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片光电二极管内存集成电路
页数 文件大小 规格书
12页 141K
描述
FIFO, 16KX9, 20ns, Asynchronous, CMOS, PDSO56

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中文翻译

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72V85L20PAI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：ObsoleteReach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.71
风险等级：5.52最长访问时间：20 ns
最大时钟频率 (fCLK)：33.3 MHzJESD-30 代码：R-PDSO-G56
JESD-609代码：e0内存密度：147456 bit
内存集成电路类型：OTHER FIFO内存宽度：9
湿度敏感等级：1端子数量：56
字数：16384 words字数代码：16000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：16KX9
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：225
电源：3.3 V认证状态：Not Qualified
最大待机电流：0.005 A子类别：FIFOs
最大压摆率：0.1 mA标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
Base Number Matches：1

72V85L20PAI 数据手册

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IDT72V81  
IDT72V82  
IDT72V83  
IDT72V84  
IDT72V85  
3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO  
DUAL 512 x 9, DUAL 1,024 x 9  
DUAL 2,048 x 9, DUAL 4,096 X 9  
DUAL 8,192 X 9  
FEATURES:  
DESCRIPTION:  
•
•
•
•
•
•
The IDT72V81 is equivalent to two IDT72V01 - 512 x 9 FIFOs  
The IDT72V82 is equivalent to two IDT72V02 - 1,024 x 9 FIFOs  
The IDT72V83 is equivalent to two IDT72V03 - 2,048 x 9 FIFOs  
The IDT72V84 is equivalent to two IDT72V04 - 4,096 x 9 FIFOs  
The IDT72V85 is equivalent to two IDT72V05 - 8,192 x 9 FIFOs  
Low power consumption  
TheIDT72V81/72V82/72V83/72V84/72V85aredual-FIFOmemoriesthat  
loadandemptydataonafirst-in/first-outbasis.Thesedevicesarefunctionaland  
compatibletotwoIDT72V01/72V02/72V03/72V04/72V05FIFOsinasingle  
packagewithallassociatedcontrol,data,andflaglinesassignedtoseparate  
pins. The devices use Full and Empty flags to prevent data overflow and  
underflowandexpansionlogictoallowforunlimitedexpansioncapabilityinboth  
word size and depth.  
— Active: 330 mW (max.)  
— Power-down: 18 mW (max.)  
Ultra high speed—15 ns access time  
Asynchronous and simultaneous read and write  
Offers optimal combination of data capacity, small foot print  
and functional flexibility  
The reads and writes are internally sequential through the use of ring  
pointers,withnoaddressinformationrequiredtoloadandunloaddata. Data  
istoggledinandoutofthedevicesthroughtheuseoftheWrite(W)andRead  
(R) pins.  
•
•
•
The devices utilize a 9-bit wide data array to allow for control and parity  
•
Ideal for bidirectional, width expansion, depth expansion, bus- bitsattheuser’soption.Thisfeatureis especiallyusefulindatacommunications  
matching, and data sorting applications  
Status Flags: Empty, Half-Full, Full  
Auto-retransmit capability  
High-performance CEMOS™ technology  
Space-saving TSSOP package  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
applicationswhereitisnecessarytouseaparitybitfortransmission/reception  
errorchecking.ItalsofeaturesaRetransmit(RT)capabilitythatallowsforreset  
of the read pointer to its initial position when RT is pulsed low to allow for  
retransmissionfromthebeginningofdata.AHalf-FullFlagisavailableinthe  
singledevicemodeandwidthexpansionmodes.  
These FIFOs are fabricated using IDT’s high-speed CMOS technology.  
Theyaredesignedforthoseapplicationsrequiringasynchronousandsimul-  
taneousread/writesinmultiprocessingandratebufferapplications.  
•
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM  
DATA INPUTS  
DATA INPUTS  
(DA  
0
-DA  
8)  
RSA  
(DB  
0
-DB  
8)  
RSB  
WB  
WRITE  
CONTROL  
WRITE  
CONTROL  
WA  
RAM  
RAM  
ARRAY A  
512 x 9  
ARRAY A  
512 x 9  
1,024 x 9  
2,048 x 9  
4,096 x 9  
8,192 x 9  
1,024 x 9  
2,048 x 9  
4,096 x 9  
8,192 x 9  
WRITE  
POINTER  
WRITE  
POINTER  
READ  
POINTER  
READ  
POINTER  
THREE-  
STATE  
BUFFERS  
THREE-  
STATE  
BUFFERS  
READ  
CONTROL  
READ  
CONTROL  
RA  
RESET  
LOGIC  
RESET  
LOGIC  
FLAG  
LOGIC  
FLAG  
LOGIC  
EXPANSION  
LOGIC  
EXPANSION  
LOGIC  
XIA  
FFA EFA  
RB  
XIB  
XOA/HFA  
FLA/RTA  
FFB EFB  
FLB/RTB  
DATA  
XOB/HFB  
DATA  
OUTPUTS  
(QB0-QB8)  
OUTPUTS  
3966 drw 01  
(QA -QA8)  
0
CIDTOandMtheMIDTElogRoaIreCtraAdemLarksTofInEtegMratePdDEevRiceATecThnUologRy,IEnc. ThReAAsynNcFIGFOEisatrademarkofIntegratedDeviceTechnology,Inc.  
JULY 2006  
1
DSC-3966/2  
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
1234567...12

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