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72V90823J PDF预览

72V90823J

更新时间: 2024-11-13 21:16:55
品牌 Logo 应用领域
艾迪悌 - IDT 电信电信集成电路
页数 文件大小 规格书
27页 204K
描述
Digital Time Switch, PQCC84, 1.150 X 1.150 INCH, 0.050 INCH PITCH, PLASTIC, LCC-84

72V90823J 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:LCC
包装说明:QCCJ, LDCC84,1.2SQ针数:84
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.6
JESD-30 代码:S-PQCC-J84JESD-609代码:e0
长度:29.31 mm湿度敏感等级:1
功能数量:1端子数量:84
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC84,1.2SQ封装形状:SQUARE
封装形式:CHIP CARRIER峰值回流温度(摄氏度):225
电源:3.3 V认证状态:Not Qualified
座面最大高度:4.57 mm子类别:Other Telecom ICs
最大压摆率:0.045 mA标称供电电压:3.3 V
表面贴装:YES电信集成电路类型:DIGITAL TIME SWITCH
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:29.31 mmBase Number Matches:1

72V90823J 数据手册

 浏览型号72V90823J的Datasheet PDF文件第2页浏览型号72V90823J的Datasheet PDF文件第3页浏览型号72V90823J的Datasheet PDF文件第4页浏览型号72V90823J的Datasheet PDF文件第5页浏览型号72V90823J的Datasheet PDF文件第6页浏览型号72V90823J的Datasheet PDF文件第7页 
3.3 VOLT TIME SLOT INTERCHANGE  
DIGITAL SWITCH  
2,048 x 2,048  
IDT72V90823  
(PQFP) and 100-pin Thin Quad Flatpack (TQFP)  
3.3V Power Supply  
Operating Temperature Range -40°C to +85°C  
FEATURES:  
2,048 x 2,048 channel non-blocking switching at 8.192 Mb/s  
Per-channel variable or constant throughput delay  
Automatic identification of ST-BUS®/GCI interfaces  
Accept streams of 2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s  
Automatic frame offset delay measurement  
Per-stream frame delay offset programming  
Per-channel high impedance output control  
Per-channel Processor Mode  
Control interface compatible to Intel/Motorola CPUs  
Connection memory block programming  
IEEE-1149.1 (JTAG) Test Port  
Available in 84-pin Plastic Leaded Chip Carrier (PLCC),  
100-pin Ball Grid Array (BGA), 100-pin Plastic Quad Flatpack  
DESCRIPTION:  
The IDT72V90823 is a non-blocking digital switch that has a capacity of  
2,048x2,048channelsataserialbitrateof8.192Mb/s,1,024x1,024channels  
at4.096Mb/sand512x512channelsat2.048Mb/s.Someofthemainfeatures  
are:programmablestreamandchannelcontrol,ProcessorMode,inputoffset  
delayandhigh-impedanceoutputcontrol.  
Per-streaminputdelaycontrolis providedformanaginglarge multi-chip  
switchesthattransportbothvoicechannelandconcatenateddatachannels.In  
addition,inputstreamscanbeindividuallycalibratedforinputframeoffset.  
FUNCTIONALBLOCKDIAGRAM  
RESET  
TRST  
VCC GND  
TMS  
TDI  
TDO TCK  
IC  
ODE  
Test Port  
Loopback  
RX0  
TX0  
TX1  
RX1  
RX2  
RX3  
TX2  
TX3  
RX4  
TX4  
Receive  
Serial Data  
Streams  
RX5  
RX6  
Transmit  
Serial Data  
Streams  
TX5  
TX6  
Output  
MUX  
RX7  
Data Memory  
TX7  
RX8  
TX8  
RX9  
TX9  
RX10  
RX11  
RX12  
RX13  
RX14  
RX15  
TX10  
TX11  
TX12  
TX13  
TX14  
TX15  
Connection  
Memory  
Internal  
Registers  
Timing Unit  
Microprocessor Interface  
DS/  
RD  
F0i  
DTA  
D8-D15/  
CLK  
FE/  
HCLK  
WFPS  
AS/ IM  
ALE  
R/W/ A0-A7  
WR  
CCO  
CS  
AD0-AD7  
5712 drw01  
February 25, 2009  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. TheST-BUSisatrademarkofMitelCorp.  
1
2002 Integrated Device Technology, Inc. All rights reserves. Product specifications subject to change without notice.  
DSC-5712/4  

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