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72V36100L10PF8 PDF预览

72V36100L10PF8

更新时间： 2024-11-25 05:31:07
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
48页 378K
描述
TQFP-128, Reel

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72V36100L10PF8 数据手册

 浏览型号72V36100L10PF8的Datasheet PDF文件第2页浏览型号72V36100L10PF8的Datasheet PDF文件第3页浏览型号72V36100L10PF8的Datasheet PDF文件第4页浏览型号72V36100L10PF8的Datasheet PDF文件第5页浏览型号72V36100L10PF8的Datasheet PDF文件第6页浏览型号72V36100L10PF8的Datasheet PDF文件第7页 
3.3 VOLT HIGH-DENSITY SUPERSYNC II™  
36-BIT FIFO  
65,536 x 36  
131,072 x 36  
IDT72V36100  
IDT72V36110  
• Empty, Full and Half-Full flags signal FIFO status  
• Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of eight preselected offsets  
• Selectable synchronous/asynchronous timing modes for Almost-  
Empty and Almost-Full flags  
• Program programmable flags by either serial or parallel means  
• Select IDT Standard timing (using EF and FF flags) or First Word  
Fall Through timing (using OR and IR flags)  
• Output enable puts data outputs into high impedance state  
• Easily expandable in depth and width  
• JTAG port, provided for Boundary Scan function (PBGA Only)  
• Independent Read and Write Clocks (permit reading and writing  
simultaneously)  
• Availableina128-pinThinQuadFlatPack(TQFP)ora144-pinPlastic  
Ball Grid Array (PBGA) (with additional features)  
• Pin compatible to the SuperSync II (IDT72V3640/72V3650/72V3660/  
72V3670/72V3680/72V3690)family  
FEATURES:  
• Choose among the following memory organizations:  
IDT72V36100 ⎯ 65,536 x 36  
IDT72V36110 ⎯ 131,072 x 36  
• Higher density, 2Meg and 4Meg SuperSync II FIFOs  
• Up to 166 MHz Operation of the Clocks  
• UserselectableAsynchronous readand/orwriteports (PBGAOnly)  
• User selectable input and output port bus-sizing  
- x36 in to x36 out  
- x36 in to x18 out  
- x36 in to x9 out  
- x18 in to x36 out  
- x9 in to x36 out  
• Big-Endian/Little-Endian user selectable byte representation  
• 5V input tolerant  
• Fixed, low first word latency  
• Zero latency retransmit  
• Auto power down minimizes standby power consumption  
• Master Reset clears entire FIFO  
• High-performance submicron CMOS technology  
• Industrial temperature range (–40°C to +85°C) is available  
• Green parts available, see ordering information  
• Partial Reset clears data, but retains programmable settings  
FUNCTIONALBLOCKDIAGRAM  
*Available on the PBGA package only.  
D0 -Dn (x36, x18 or x9)  
LD SEN  
WEN  
WCLK/WR  
*
INPUT REGISTER  
OFFSET REGISTER  
FF/IR  
PAF  
EF/OR  
FLAG  
LOGIC  
PAE  
HF  
FWFT/SI  
PFM  
FSEL0  
FSEL1  
WRITE CONTROL  
LOGIC  
ASYW  
*
RAM ARRAY  
65,536 x 36  
131,072 x 36  
WRITE POINTER  
READ POINTER  
BE  
CONTROL  
LOGIC  
IP  
RT  
RM  
ASYR  
READ  
CONTROL  
LOGIC  
BM  
IW  
OW  
OUTPUT REGISTER  
BUS  
*
CONFIGURATION  
MRS  
PRS  
RESET  
LOGIC  
RCLK/RD  
*
REN  
TCK  
*
*
TRST  
TMS  
TDI  
TDO  
JTAG CONTROL  
(BOUNDARY  
SCAN)  
*
6117 drw01  
*
Q0 -Qn (x36, x18 or x9)  
OE  
*
*
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSuperSyncIIFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
OCTOBER 2008  
1
©
2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-6117/14  
1234567...48

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72V36100L10PF8 替代型号

型号 品牌 替代类型 描述 数据表
72V36100L10PFG IDT

功能相似

 3.3 VOLT HIGH-DENSITY SUPERSYNC II
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72V36100L15BBG IDT

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72V36100L15BBG8 IDT

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72V36100L15BBGI IDT

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72V36100L15PFG IDT

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