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72T1845L6-7BBGI PDF预览

72T1845L6-7BBGI

更新时间: 2024-12-01 19:00:11
品牌 Logo 应用领域
艾迪悌 - IDT LTE先进先出芯片
页数 文件大小 规格书
55页 510K
描述
FIFO, 2KX18, 3.8ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144

72T1845L6-7BBGI 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:144
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.84
Is Samacsys:N最长访问时间:3.8 ns
其他特性:ALTERNATIVE MEMORY WIDTH 9; ASYNCHRONOUS OPERATION ALSO POSSIBLE周期时间:6.7 ns
JESD-30 代码:S-PBGA-B144JESD-609代码:e1
长度:13 mm内存密度:36864 bit
内存宽度:18湿度敏感等级:3
功能数量:1端子数量:144
字数:2048 words字数代码:2000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:2KX18
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.97 mm最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:13 mmBase Number Matches:1

72T1845L6-7BBGI 数据手册

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2.5 VOLT HIGH-SPEED TeraSync™ FIFO  
18-BIT/9-BITCONFIGURATIONS  
2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9,  
16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,  
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9, 524,288 x 18/1,048,576 x 9  
IDT72T1845, IDT72T1855  
IDT72T1865, IDT72T1875  
IDT72T1885, IDT72T1895  
IDT72T18105, IDT72T18115  
IDT72T18125  
Empty and Almost-Full flags  
FEATURES:  
Separate SCLK input for Serial programming of flag offsets  
User selectable input and output port bus-sizing  
- x9 in to x9 out  
- x9 in to x18 out  
- x18 in to x9 out  
Choose among the following memory organizations:  
IDT72T1845  
IDT72T1855  
IDT72T1865  
IDT72T1875  
IDT72T1885  
IDT72T1895  
IDT72T18105  
IDT72T18115  
IDT72T18125  
2,048 x 18/4,096 x 9  
4,096 x 18/8,192 x 9  
8,192 x 18/16,384 x 9  
16,384 x 18/32,768 x 9  
32,768 x 18/65,536 x 9  
65,536 x 18/131,072 x 9  
131,072 x 18/262,144 x 9  
262,144 x 18/524,288 x 9  
524,288 x 18/1,048,576 x 9  
- x18 in to x18 out  
Big-Endian/Little-Endian user selectable byte representation  
Auto power down minimizes standby power consumption  
Master Reset clears entire FIFO  
Partial Reset clears data, but retains programmable settings  
Empty, Full and Half-Full flags signal FIFO status  
Select IDT Standard timing (using EF and FF flags) or First Word  
Fall Through timing (using OR and IR flags)  
Output enable puts data outputs into high impedance state  
JTAG port, provided for Boundary Scan function  
Available in 144-pin (13mm x 13mm) or 240-pin (19mm x 19mm)  
PlasticBallGridArray(PBGA)  
Easily expandable in depth and width  
Independent Read and Write Clocks (permit reading and writing  
simultaneously)  
High-performance submicron CMOS technology  
Industrial temperature range (–40°C to +85°C) is available  
Green parts are available, see ordering information  
Up to 225 MHz Operation of Clocks  
User selectable HSTL/LVTTL Input and/or Output  
Read Enable & Read Clock Echo outputs aid high speed operation  
User selectable Asynchronous read and/or write port timing  
2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage  
3.3V Input tolerant  
Mark & Retransmit, resets read pointer to user marked position  
Write Chip Select (WCS) input enables/disables Write operations  
Read Chip Select (RCS) synchronous to RCLK  
Programmable Almost-Empty and Almost-Full flags, each flag can  
default to one of eight preselected offsets  
Program programmable flags by either serial or parallel means  
Selectable synchronous/asynchronous timing modes for Almost-  
FUNCTIONALBLOCKDIAGRAM  
D0 -Dn (x18 or x9)  
LD SEN  
SCLK  
WEN  
WCLK/WR  
WCS  
INPUT REGISTER  
OFFSET REGISTER  
FF/IR  
PAF  
EF/OR  
PAE  
HF  
FWFT/SI  
PFM  
FSEL0  
FSEL1  
WRITE CONTROL  
LOGIC  
ASYW  
FLAG  
LOGIC  
RAM ARRAY  
2,048 x 18 or 4,096 x 9  
4,096 x 18 or 8,192 x 9  
WRITE POINTER  
8,192 x 18 or 16,384 x 9  
16,384 x 18 or 32,768 x 9  
32,768 x 18 or 65,536 x 9  
65,536 x 18 or 131,072 x 9  
131,072 x 18 or 262,144 x 9  
262,144 x 18 or 524,288 x 9  
524,288 x 18 or 1,048,576 x 9  
BE  
CONTROL  
LOGIC  
READ POINTER  
IP  
IW  
BUS  
CONFIGURATION  
OW  
RT  
READ  
CONTROL  
LOGIC  
MARK  
ASYR  
MRS  
PRS  
OUTPUT REGISTER  
RESET  
LOGIC  
TCK  
TRST  
TMS  
TDO  
JTAG CONTROL  
(BOUNDARY SCAN)  
RCLK/RD  
REN  
RCS  
TDI  
Vref  
WHSTL  
RHSTL  
SHSTL  
HSTL I/0  
CONTROL  
EREN  
OE  
5909 drw01  
Q0 -Qn (x18 or x9)  
ERCLK  
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. TeraSync FIFO is a trademark of Integrated Device Technology, Inc.  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
FEBRUARY 2009  
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-5909/19  

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