Datasheet > 72T1865L4-4BBI

72T1865L4-4BBI

更新时间： 2024-12-01 15:46:11

品牌	Logo	应用领域
艾迪悌 - IDT		时钟先进先出芯片内存集成电路
页数	文件大小	规格书
51页	393K
描述
FIFO, 8KX18, 8ns, Synchronous/Asynchronous, CMOS, PBGA144

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技术参数
数据手册

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72T1865L4-4BBI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	BGA, BGA144,12X12,40	Reach Compliance Code：	not_compliant
风险等级：	5.92	最长访问时间：	8 ns
备用内存宽度：	9	最大时钟频率 (fCLK)：	100 MHz
JESD-30 代码：	S-PBGA-B144	JESD-609代码：	e0
内存密度：	147456 bit	内存集成电路类型：	OTHER FIFO
内存宽度：	18	湿度敏感等级：	3
端子数量：	144	字数：	8192 words
字数代码：	8000	工作模式：	SYNCHRONOUS/ASYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	8KX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装等效代码：	BGA144,12X12,40
封装形状：	SQUARE	封装形式：	GRID ARRAY
电源：	2.5 V	认证状态：	Not Qualified
最大待机电流：	0.05 A	子类别：	FIFOs
最大压摆率：	0.06 mA	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn63Pb37)
端子形式：	BALL	端子节距：	1 mm
端子位置：	BOTTOM	Base Number Matches：	1

72T1865L4-4BBI 数据手册

2.5 VOLT HIGH-SPEED TeraSync™ FIFO

PRELIMINARY

IDT72T1845, IDT72T1855

IDT72T1865, IDT72T1875

IDT72T1885, IDT72T1895

IDT72T18105, IDT72T18115

IDT72T18125

18-BIT/9-BITCONFIGURATIONS

2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9,

16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,

131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9, 524,288 x 18/1,048,576 x 9

Empty and Almost-Full flags

FEATURES:

• Separate SCLK input for Serial programming of flag offsets

• User selectable input and output port bus-sizing

- x9 in to x9 out

- x9 in to x18 out

- x18 in to x9 out

• Choose among the following memory organizations:

IDT72T1845

IDT72T1855

IDT72T1865

IDT72T1875

IDT72T1885

IDT72T1895

IDT72T18105

IDT72T18115

IDT72T18125

2,048 x 18/4,096 x 9

4,096 x 18/8,192 x 9

8,192 x 18/16,384 x 9

16,384 x 18/32,768 x 9

32,768 x 18/65,536 x 9

65,536 x 18/131,072 x 9

131,072 x 18/262,144 x 9

262,144 x 18/524,288 x 9

524,288 x 18/1,048,576 x 9

- x18 in to x18 out

• Big-Endian/Little-Endian user selectable byte representation

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable settings

• Empty, Full and Half-Full flags signal FIFO status

• Select IDT Standard timing (using EF and FF flags) or First Word

Fall Through timing (using OR and IR flags)

• Output enable puts data outputs into high impedance state

• JTAG port, provided for Boundary Scan function

• Available in 144-pin (13mm x 13mm) or 240-pin (19mm x 19mm)

PlasticBallGridArray(PBGA)

• Easily expandable in depth and width

• Independent Read and Write Clocks (permit reading and writing

simultaneously)

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

• Up to 225 MHz Operation of Clocks

• User selectable HSTL/LVTTL Input and/or Output

• Read Enable & Read Clock Echo outputs aid high speed operation

• User selectable Asynchronous read and/or write port timing

• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage

• 3.3V Input tolerant

• Mark & Retransmit, resets read pointer to user marked position

• Write Chip Select (WCS) input enables/disables Write operations

• Read Chip Select (RCS) synchronous to RCLK

• Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of eight preselected offsets

• Program programmable flags by either serial or parallel means

• Selectable synchronous/asynchronous timing modes for Almost-

FUNCTIONALBLOCKDIAGRAM

D0 -Dn (x18 or x9)

LD SEN

SCLK

WEN

WCLK/WR

WCS

INPUT REGISTER

OFFSET REGISTER

FF/IR

PAF

EF/OR

PAE

FWFT/SI

PFM

FSEL0

FSEL1

WRITE CONTROL

LOGIC

ASYW

FLAG

LOGIC

RAM ARRAY

2,048 x 18 or 4,096 x 9

4,096 x 18 or 8,192 x 9

WRITE POINTER

8,192 x 18 or 16,384 x 9

16,384 x 18 or 32,768 x 9

32,768 x 18 or 65,536 x 9

65,536 x 18 or 131,072 x 9

131,072 x 18 or 262,144 x 9

262,144 x 18 or 524,288 x 9

524,288 x 18 or 1,048,576 x 9

CONTROL

LOGIC

READ POINTER

BUS

CONFIGURATION

READ

CONTROL

LOGIC

MARK

MRS

PRS

OUTPUT REGISTER

RESET

LOGIC

ASYR

TCK

TRST

TMS

TDO

JTAG CONTROL

(BOUNDARY SCAN)

RCLK/RD

REN

RCS

TDI

Vref

WHSTL

RHSTL

SHSTL

HSTL I/0

CONTROL

EREN

5909 drw01

Q0 -Qn (x18 or x9)

ERCLK

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. TeraSync FIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

NOVEMBER 2001

DSC-5909/9

12 3 4 5 6 7...51

中文翻译

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与72T1865L4-4BBI相关器件

型号	品牌	获取价格	描述	数据表
72T1865L5BBG	IDT	获取价格	FIFO, 8KX18, 3.6ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144
72T1865L6-7BBG	IDT	获取价格	FIFO, 8KX18, 3.8ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144
72T1865L6-7BBGI	IDT	获取价格	FIFO, 8KX18, 3.8ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144
72T1875L10BBG	IDT	获取价格	FIFO, 16KX18, 4.5ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144
72T1875L4-4BBG	IDT	获取价格	FIFO, 16KX18, 3.4ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144
72T1875L4-4BBGI	IDT	获取价格	FIFO, 16KX18, 3.4ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144
72T1875L4-4BBI	IDT	获取价格	FIFO, 16KX18, 8ns, Synchronous/Asynchronous, CMOS, PBGA144
72T1875L5BBGI	IDT	获取价格	FIFO, 16KX18, 3.6ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144
72T1875L6-7BBG	IDT	获取价格	FIFO, 16KX18, 3.8ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144
72T1875L6-7BBGI	IDT	获取价格	FIFO, 16KX18, 3.8ns, Synchronous, CMOS, PBGA144, 13 X 13 MM, 1 MM PITCH, PLASTIC, BGA-144

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