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72420L10TPG PDF预览

72420L10TPG

更新时间: 2024-11-12 01:19:19
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片光电二极管内存集成电路
页数 文件大小 规格书
11页 258K
描述
CMOS SyncFIFO

72420L10TPG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:PDIP
包装说明:DIP, DIP28,.3针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.56
最长访问时间:6.5 ns最大时钟频率 (fCLK):100 MHz
周期时间:10 nsJESD-30 代码:R-PDIP-T28
JESD-609代码:e3长度:34.67 mm
内存密度:512 bit内存集成电路类型:OTHER FIFO
内存宽度:8湿度敏感等级:1
功能数量:1端子数量:28
字数:64 words字数代码:64
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64X8
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP28,.3
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:4.57 mm最大待机电流:0.005 A
子类别:FIFOs最大压摆率:0.04 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn) - annealed端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

72420L10TPG 数据手册

 浏览型号72420L10TPG的Datasheet PDF文件第2页浏览型号72420L10TPG的Datasheet PDF文件第3页浏览型号72420L10TPG的Datasheet PDF文件第4页浏览型号72420L10TPG的Datasheet PDF文件第5页浏览型号72420L10TPG的Datasheet PDF文件第6页浏览型号72420L10TPG的Datasheet PDF文件第7页 
IDT72420  
IDT72200  
IDT72210  
IDT72220  
IDT72230  
IDT72240  
CMOS SyncFIFO™  
64 x 8, 256 x 8,  
512 x 8, 1,024 x 8,  
2,048 x 8 and 4,096 x 8  
FEATURES:  
DESCRIPTION:  
64 x 8-bit organization (IDT72420)  
TheIDT72420/72200/72210/72220/72230/72240SyncFIFOarevery  
high-speed,low-powerFirst-In,First-Out(FIFO)memorieswithclocked read  
andwritecontrols.Thesedeviceshavea64,256,512,1,024,2,048,and4,096  
x 8-bit memory array, respectively. These FIFOs are applicable for a wide  
varietyofdatabufferingneeds,suchasgraphics,LocalAreaNetworks(LANs),  
andinterprocessorcommunication.  
256 x 8-bit organization (IDT72200)  
512 x 8-bit organization (IDT72210)  
1,024 x 8-bit organization (IDT72220)  
2,048 x 8-bit organization (IDT72230)  
4,096 x 8-bit organization (IDT72240)  
10 ns read/write cycle time (IDT72420/72200/72210/72220/72230/  
72240)  
Read and Write Clocks can be asynchronous or coincidental  
Dual-Ported zero fall-through time architecture  
Empty and Full flags signal FIFO status  
Almost-Empty and Almost-Full flags set to Empty+7 and Full-7,  
respectively  
Output enable puts output data bus in high-impedance state  
Produced with advanced submicron CMOS technology  
Available in 28-pin 300 mil plastic DIP  
For surface mount product please see the IDT72421/72201/72211/ forimprovedsystemcontrol.Thepartial(AE)flagsaresettoEmpty+7andFull-  
72221/72231/72241 data sheet  
TheseFIFOshave8-bitinputandoutputports.Theinputportiscontrolled  
byafree-runningclock(WCLK),andaWriteEnablepin(WEN). Dataiswritten  
intotheSynchronousFIFOoneveryclockwhenWENisasserted.Theoutput  
portiscontrolledbyanotherclockpin(RCLK)andaReadEnablepin(REN).  
TheReadClockcanbetiedtotheWriteClockforsingleclockoperationorthe  
twoclockscanrunasynchronousofoneanotherfordualclockoperation.An  
OutputEnablepin(OE)isprovidedonthereadportforthree-statecontrolof  
theoutput.  
These Synchronous FIFOs have two endpoint flags, Empty (EF) and Full  
(FF).Twopartialflags,Almost-Empty(AE)andAlmost-Full(AF),areprovided  
7 for AE and AF respectively.  
TheseFIFOsarefabricatedusinghigh-speedsubmicronCMOStechnol-  
ogy.  
Green parts available, see ordering information  
FUNCTIONAL BLOCK DIAGRAM  
D0 - D7  
WCLK  
WEN  
INPUT REGISTER  
EF  
AE  
AF  
FF  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
RAM ARRAY  
64 x 8, 256 x 8,  
512 x 8, 1,024 x 8,  
2,048 x 8, 4,096 x 8  
WRITE POINTER  
READ POINTER  
READ CONTROL  
LOGIC  
OUTPUT REGISTER  
RESET LOGIC  
RCLK  
RS  
REN  
OE  
2680 drw01  
Q0 - Q7  
CIDTO,IDTMlogMoarEereRgisCtereIdAtraLdemaTrksEofIMntegPratEedDRevAiceTTeUchnRologEy,IncR.ThAeSNyncGFIFEOisatrademarkofIntegratedDeviceTechnology,Inc.  
JULY 2013  
1
©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-2680/6  

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