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723616L20PFI8 PDF预览

723616L20PFI8

更新时间: 2024-11-20 08:27:39
品牌 Logo 应用领域
艾迪悌 - IDT 时钟先进先出芯片内存集成电路
页数 文件大小 规格书
26页 203K
描述
TQFP-128, Reel

723616L20PFI8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:TQFP
包装说明:TQFP-128针数:128
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.9
最长访问时间:12 ns其他特性:PARITY GENERATOR/CHECKER; ONE BIDIRECTIONAL 36-BIT PORT AND TWO UNIDIRECTIONAL 18-BIT PORTS
最大时钟频率 (fCLK):50 MHz周期时间:20 ns
JESD-30 代码:R-PQFP-G128JESD-609代码:e0
长度:20 mm内存密度:2304 bit
内存集成电路类型:BI-DIRECTIONAL FIFO内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:128字数:64 words
字数代码:64工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:64X36可输出:YES
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP128,.63X.87,20封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.001 A子类别:FIFOs
最大压摆率:0.001 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn85Pb15)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

723616L20PFI8 数据手册

 浏览型号723616L20PFI8的Datasheet PDF文件第2页浏览型号723616L20PFI8的Datasheet PDF文件第3页浏览型号723616L20PFI8的Datasheet PDF文件第4页浏览型号723616L20PFI8的Datasheet PDF文件第5页浏览型号723616L20PFI8的Datasheet PDF文件第6页浏览型号723616L20PFI8的Datasheet PDF文件第7页 
CMOS TRIPLE BUS SyncFIFO™  
WITH BUS-MATCHING AND  
BYTE SWAPPING 64 x 36 x 2  
IDT723616  
Width can be easily expanded by adding FIFOs  
Auto power down minimizes power dissipation  
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)  
High performance sub-micron CMOS technology  
Industrial temperature range (–40oC to +85oC) is available  
Green parts available, see ordering information  
FEATURES:  
Two independent FIFOs (64 X 36 storage capacity each) buffer  
data between bidirectional 36-bit port A and two unidirectional  
18/9-bit ports (Port B transmits, Port C receives)  
Clock frequencies up to 67 MHz (10 ns access time)  
Free-running clock lines for each port: CLKA, CLKB and CLKC,  
may be asynchronous or coincident (simultaneous reading and  
writing of data is permitted)  
DESCRIPTION:  
IDT Standard timing  
TheIDT723616isamonolithic,high-speed,low-power,CMOSTripleBus  
SyncFIFO(clocked) memory which supports clock frequencies up to 67  
MHzandhas readaccess times as fastas 10ns. Twoindependent64x36  
dual-portSRAMFIFOsonboardeachchipbufferdatabetweenabidirectional  
36-bitbus(PortA)andtwounidirectional18-bitbuses(PortBtransmitsdata,  
PortCreceives data.)FIFOdata canbe readoutofports Bandwritteninto  
portCusingeither18-bitor9-bitformats.  
Empty flag functions: EFA (synchronized by CLKA) and EFB  
(synchronized by CLKB)  
Full flag functions: FFA (synchronized by CLKA) and FFC  
(synchronized by CLKC)  
Programmable Almost-Empty and Almost-Full flags; each has  
four default offsets (4, 8, 12 and 16)  
Bus sizing of 18-bits (word) and 9-bits (byte) for ports B and C  
Byte order swapping on ports B and C  
Passive parity checking on ports A and C  
Parity generation can be selected for ports A and B  
Master Reset clears data and configures FIFO  
Reset(RST)initializesthereadandwritepointerstothefirstlocationofthe  
memoryarrayandselectsoneoffourpossibledefaultflagoffsetsettings:4,8,  
12 or 16.  
EachFIFOhasflagstoindicateemptyandfullconditionsandtwoprogram-  
mable flags (Almost-Full and Almost-Empty) to indicate when a selected  
FUNCTIONALBLOCKDIAGRAM  
CLKA  
PGB  
Port-A  
CSA  
Control  
W/RA  
ENA  
Logic  
RAM  
ARRAY  
18  
B0 - B17  
Parity  
check  
64 x 36  
PEFA  
Port-B  
Control  
Logic  
CLKB  
RENB  
Write  
Pointer  
Read  
Pointer  
36  
FFA  
AFA  
Status Flag  
Logic  
EFB  
AEB  
FIFO 1  
FIFO 2  
SWB0  
SWB1  
SWC0  
SWC1  
SIZ0  
Common  
Port  
Programmable Flag  
Offset Registers  
Control  
Logic  
FS0  
FS1  
- A35  
(B and C)  
A
0
SIZ1  
EFA  
AEA  
Status Flag  
Logic  
FFC  
AFC  
Read  
Pointer  
Write  
Pointer  
36  
FIFO2,  
FIFO1  
Reset/  
Control  
Logic  
Parity  
RST  
PEFC  
Check  
ODD/EVEN  
RAM  
ARRAY  
18  
C0 - C17  
64 x 36  
CLKC  
Port-C  
Control  
Logic  
WENC  
PGA  
3520 drw01  
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.  
FEBRUARY 2009  
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES  
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-3107/3  

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