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72231L15JG PDF预览

72231L15JG

更新时间: 2024-11-05 20:55:27
品牌 Logo 应用领域
艾迪悌 - IDT 先进先出芯片内存集成电路
页数 文件大小 规格书
14页 286K
描述
FIFO, 2KX9, 10ns, Synchronous, CMOS, PQCC32, GREEN, PLASTIC, LCC-32

72231L15JG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:QFJ
包装说明:LCC-32针数:32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.71风险等级:5.1
最长访问时间:10 ns周期时间:15 ns
JESD-30 代码:R-PLCC-J32JESD-609代码:e3
内存密度:18432 bit内存集成电路类型:OTHER FIFO
内存宽度:9湿度敏感等级:1
功能数量:1端子数量:32
字数:2048 words字数代码:2000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2KX9
输出特性:3-STATE可输出:YES
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
最大待机电流:0.005 A子类别:FIFOs
最大压摆率:0.035 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:J BEND端子位置:QUAD
处于峰值回流温度下的最长时间:30Base Number Matches:1

72231L15JG 数据手册

 浏览型号72231L15JG的Datasheet PDF文件第2页浏览型号72231L15JG的Datasheet PDF文件第3页浏览型号72231L15JG的Datasheet PDF文件第4页浏览型号72231L15JG的Datasheet PDF文件第5页浏览型号72231L15JG的Datasheet PDF文件第6页浏览型号72231L15JG的Datasheet PDF文件第7页 
CMOSSyncFIFO™  
64 x 9, 256 x 9, 512 x 9,  
1,024 x 9, 2,048 x 9,  
4,096 x 9 and 8,192 x 9  
IDT72421,IDT72201  
IDT72211,IDT72221  
IDT72231,IDT72241  
IDT72251  
FEATURES:  
DESCRIPTION:  
64 x 9-bit organization (IDT72421)  
The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFO™  
256 x 9-bit organization (IDT72201)  
512 x 9-bit organization (IDT72211)  
1,024 x 9-bit organization (IDT72221)  
2,048 x 9-bit organization (IDT72231)  
4,096 x 9-bit organization (IDT72241)  
8,192 x 9-bit organization (IDT72251)  
10 ns read/write cycle time  
Read and Write Clocks can be independent  
Dual-Ported zero fall-through time architecture  
Empty and Full Flags signal FIFO status  
Programmable Almost-Empty and Almost-Full flags can be set  
to any depth  
are very high-speed, low-power First-In, First-Out (FIFO) memories with  
clocked read and write controls. These devices have a 64, 256, 512, 1,024,  
2,048,4,096,and8,192x9-bitmemoryarray,respectively. TheseFIFOsare  
applicableforawidevarietyofdatabufferingneedssuchasgraphics,localarea  
networksandinterprocessorcommunication.  
TheseFIFOshave9-bitinputandoutputports.Theinputportiscontrolled  
byafree-runningclock(WCLK),andtwowriteenablepins(WEN1,WEN2).  
Data is written into the Synchronous FIFO on every rising clock edge when  
thewriteenablepinsareasserted.Theoutputportiscontrolledbyanotherclock  
pin (RCLK) and two read enable pins (REN1, REN2). The Read Clock can  
betiedtotheWriteClockforsingleclockoperationorthetwoclockscanrun  
asynchronousofoneanotherfordual-clockoperation.Anoutputenablepin  
(OE) is provided on the read port for three-state control of the output.  
TheSynchronousFIFOshavetwofixedflags,Empty(EF)andFull(FF).  
Twoprogrammableflags, Almost-Empty(PAE)andAlmost-Full(PAF), are  
provided for improved system control. The programmable flags default to  
Empty+7andFull-7forPAEandPAF,respectively.Theprogrammableflag  
offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting  
Programmable Almost-Empty and Almost-Full flags default to  
Empty+7, and Full-7, respectively  
Output enable puts output data bus in high-impedance state  
Advanced submicron CMOS technology  
Available in the 32-pin plastic leaded chip carrier (PLCC) and  
32-pin Thin Quad Flat Pack (TQFP)  
For through-hole product please see the IDT72420/72200/72210/ the load pin (LD).  
72220/72230/72240 data sheet  
TheseFIFOsarefabricatedusinghigh-speedsubmicronCMOStechnology.  
Industrial temperature range (–40°C to +85°C) is available  
Green parts available, see ordering information  
FUNCTIONAL BLOCK DIAGRAM  
D0 - D8  
WCLK  
WEN1  
WEN2  
LD  
OFFSET REGISTER  
INPUT REGISTER  
EF  
FLAG  
LOGIC  
WRITE CONTROL  
LOGIC  
PAE  
PAF  
FF  
RAM ARRAY  
64 x 9, 256 x 9,  
512 x 9, 1,024 x 9,  
2,048 x 9, 4,096 x 9,  
8,192 x 9  
WRITE POINTER  
READ POINTER  
READ CONTROL  
LOGIC  
OUTPUT REGISTER  
RESET LOGIC  
RCLK  
REN1  
REN2  
RS  
2655 drw01  
OE  
Q0 - Q8  
CIDTOandMtheMIDTElogRoaCrerIegAisteLredtrAadeNmaDrksofIInNtegrDateUdDSeviTceTRecIhnAoloLgy,InTc.TEheMSynPcFEIFORisaAreTgistUereRdtraEdemaRrkoAfInNtegGrateEdDSeviceTechnology,Inc.  
AUGUST 2013  
1
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.  
DSC-2655/6  
©

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