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71V65602S100PFGI8 PDF预览

71V65602S100PFGI8

更新时间： 2024-11-29 15:40:43
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
26页 970K
描述
TQFP-100, Reel

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71V65602S100PFGI8 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：TQFP
包装说明：LQFP,针数：100
Reach Compliance Code：unknown风险等级：5.79
Is Samacsys：N最长访问时间：5 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：9437184 bit内存集成电路类型：ZBT SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX36
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

71V65602S100PFGI8 数据手册

 浏览型号71V65602S100PFGI8的Datasheet PDF文件第2页浏览型号71V65602S100PFGI8的Datasheet PDF文件第3页浏览型号71V65602S100PFGI8的Datasheet PDF文件第4页浏览型号71V65602S100PFGI8的Datasheet PDF文件第5页浏览型号71V65602S100PFGI8的Datasheet PDF文件第6页浏览型号71V65602S100PFGI8的Datasheet PDF文件第7页 
256K x 36, 512K x 18  
IDT71V65602  
IDT71V65802  
3.3VSynchronousZBT™SRAMs  
2.5V I/O, Burst Counter  
PipelinedOutputs  
Features  
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock  
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.  
The IDT71V65602/5802 contain data I/O, address and control signal  
registers.Outputenableistheonlyasynchronoussignalandcanbeusedto  
disabletheoutputsatanygiventime.  
A Clock Enable (CEN) pin allows operation of the IDT71V65602/5802  
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored  
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious  
values.  
There are three chip enable pins (CE1, CE2, CE2) that allow the  
usertodeselectthedevicewhendesired. Ifanyoneofthesethreearenot  
assertedwhenADV/LDislow, nonewmemoryoperationcanbeinitiated.  
However,anypendingdatatransfers(readsorwrites)willbecompleted.The  
databuswilltri-statetwocyclesafterchipisdeselectedorawriteisinitiated.  
The IDT71V65602/5802 have an on-chip burst counter. In the burst  
mode, the IDT71V65602/5802 can provide four cycles of data for a single  
addresspresentedtotheSRAM.Theorderoftheburstsequenceisdefined  
bytheLBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst  
sequence.TheADV/LDsignalisusedtoloadanewexternaladdress(ADV/  
LD=LOW) orincrementtheinternalburstcounter(ADV/LD=HIGH).  
The IDT71V65602/5802 SRAM utilize IDT's latest high-performance  
◆
256K x 36, 512K x 18 memory configurations  
◆
Supports high performance system speed - 150MHz  
(3.8ns Clock-to-Data Access)  
ZBT Feature - No dead cycles between write and read cycles  
Internally synchronized output buffer enable eliminates the  
◆
◆
TM  
need to control OE  
Single R/W (READ/WRITE) control pin  
◆
◆
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%)  
2.5V I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Packaged in a JEDEC standard 100-pin plastic thin quad and  
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch  
ball grid array (fBGA)  
◆
◆
◆
◆
◆
◆
◆
Description  
The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100-  
(9Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead pinthinplasticquadflatpack(TQFP)aswellasa119ballgridarray(BGA)  
bus cycles when turning the bus around between reads and writes, or and a 165 fine pitch ball grid array (fBGA).  
TM  
writes andreads.Thus,theyhavebeengiventhenameZBT ,orZero  
Bus Turnaround.  
PinDescriptionSummary  
A0-A18  
Address Inputs  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
Input  
I/O  
Synchronous  
Synchronous  
Asynchronous  
Synchronous  
Synchronous  
Synchronous  
N/A  
Chip Enables  
CE1, CE2, CE2  
Output Enable  
OE  
R/W  
Read/Write Signal  
Clock Enable  
CEN  
Individual Byte Write Selects  
Clock  
BW1, BW2, BW3, BW4  
CLK  
ADV/LD  
Advance burstaddress / Load new address  
Linear / Interleaved Burst Order  
Sleep Mode  
Synchronous  
Static  
LBO  
ZZ  
Asynchronous  
Synchronous  
Static  
I/O0-I/O31, I/OP1-I/OP4  
VDD, VDDQ  
Data Input / Output  
Core Power, I/O Power  
Ground  
Supply  
Supply  
VSS  
Static  
5303 tbl 01  
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.  
OCTOBER 2004  
1
©2004IntegratedDeviceTechnology,Inc.  
DSC-5303/05  
1234567...26

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71V65602S100PFI8 IDT

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71V65602S133BQ IDT

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 		CABGA-165, Tray
71V65602S133BQ ROCHESTER

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 		256KX36 ZBT SRAM, 4.2ns, PBGA165, 13 X 15 MM, FPBGA-165
71V65602S133BQ8 IDT

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 		CABGA-165, Reel
71V65602S133BQG IDT

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 		CABGA-165, Tray
71V65602S133BQGI IDT

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 		ZBT SRAM, 256KX36, 4.2ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
71V65602S133BQI IDT

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 		ZBT SRAM, 256KX36, 4.2ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165
71V65602S133PF ROCHESTER

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 		256KX36 ZBT SRAM, 4.2ns, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
71V65602S133PF9 IDT

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 		TQFP-100, Tray
71V65602S133PFG8 IDT

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 		TQFP-100, Reel

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