IDT71V416S
IDT71V416L
3.3V CMOS Static RAM
4 Meg (256K x 16-Bit)
Features
Description
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256K x 16 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise.
Equal access and cycle times
TheIDT71V416isa4,194,304-bithigh-speedStaticRAMorganized
as 256K x 16. It is fabricated using high-performance, high-reliability
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-
speed memory needs.
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– CommercialandIndustrial:10/12/15ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
LVTTL-compatible
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TheIDT71V416hasanoutputenablepinwhichoperatesasfastas
5ns,withaddressaccesstimesasfastas10ns.Allbidirectionalinputsand
outputsoftheIDT71V416areLVTTL-compatibleandoperationisfroma
single3.3Vsupply.Fullystaticasynchronouscircuitryisused,requiring
no clocks or refresh for operation.
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Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Single 3.3V power supply
Available in 44-pin, 400 mil plastic SOJ package and a 44-
pin, 400 mil TSOP Type II package and a 48 ball grid array,
9mmx9mmpackage.
The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a
44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x
9mmpackage.
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Green parts available, see ordering information
FunctionalBlockDiagram
Output
Enable
Buffer
OE
Address
Buffers
Row / Column
Decoders
A0 - A17
High
8
8
8
8
Byte
I/O 15
I/O 8
Output
Chip
Select
Buffer
Buffer
CS
High
Byte
Write
Sense
Amps
and
Write
Drivers
4,194,304-bit
Memory
Array
Buffer
16
Write
Enable
Buffer
Low
Byte
8
8
8
8
WE
I/O 7
I/O 0
Output
Buffer
Low
Byte
Write
Buffer
BHE
BLE
Byte
Enable
Buffers
3624 drw 01
NOVEMBER 2016
1
©2016 Integrated Device Technology, Inc.
DSC-3624/11