Datasheet > 71V3557SA85BQG8

71V3557SA85BQG8

更新时间： 2024-02-15 22:43:56

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
28页	523K
描述
SRAM

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

71V3557SA85BQG8 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

71V3557SA85BQG8 数据手册

IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with

ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs

Commercial and Industrial Temperature Ranges

Synchronous Truth Table ⁽¹⁾

CEN

CE1

CE2

BWx

R/W

ADV/LD

ADDRESS

USED

PREVIOUS CYCLE

CURRENT CYCLE

I/O

(5 )

(One cycle later)

(7 )

Valid

External

Internal

LOAD WRITE

LOAD READ

(7 )

Valid

LOAD WRITE /

BURST WRITE

(Advance burst counter)^{(2 )}

(7 )

Internal

LOAD READ /

BURST READ

(Advance burst counter)^{(2 )}

DESELECT or STOP^{(3 )}

NOOP

HIZ

DESELECT / NOOP

(4 )

SUSPEND

Previous Value

5282 tbl 08

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of

the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.

3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will

tri-state one cycle after deselect is initiated.

4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/

Os remains unchanged.

5. To select the chip requires CE¹= L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.

6. Device Outputs are ensured to be in High-Z during device power-up.

7. Q - data read from the device, D - data written to the device.

Partial Truth Table for Writes ⁽¹⁾

(3 )

BW1

BW2

BW3

BW4

OPERATION

R/W

READ

WRITE ALLBYTES

WRITE BYTE 1 (I/O[0:7], I/O^P1)

(2 )

WRITE BYTE 2 (I/O[8:15], I/O^P2)

(2,3)

WRITE BYTE 3 (I/O[16:23], I/O^P3)

(2,3)

WRITE BYTE 4 (I/O[24:31], I/O^P4)

NO WRITE

5282 tbl 09

NOTES:

1. L = VIL, H = VIH, X = Don’t Care.

2. Multiple bytes may be selected during the same cycle.

3. N/A for x18 configuration.

InterleavedBurstSequenceTable(LBO=VDD)

Sequence 1

Sequence 2

Sequence 3

Sequence 4

First Address

Second Address

Third Address

Fourth Address⁽¹⁾

5282 tbl 10

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

6.42

1...6 7 8910 11 12...28

下载PDF

与71V3557SA85BQG8相关器件

型号	品牌	描述	获取价格	数据表
71V3557SA85BQGI	IDT	Cache SRAM, 128KX36, 8.5ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165	获取价格
71V3557SA85BQGI8	IDT	SRAM	获取价格
71V3557SA85BQI	IDT	ZBT SRAM, 128KX36, 8.5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165	获取价格
71V3557SA85BQI8	IDT	SRAM	获取价格
71V3557SA85PFGI	IDT	Cache SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100	获取价格
71V3558	RENESAS	3.3V 256K x 18 ZBT Synchronous PipeLined SRAM w/3.3V I/O	获取价格

与71V3557SA85BQG8相关文章

SG3525资料手册详解：SG3525参数分析、引脚说明、应用介绍
2024-05-23

2
AT89C51单片机资料手册详细解析及应用示例
2024-05-23

5
CP2102资料手册解读：CP2102引脚说明、关键参数分析
2024-05-23

3
资料手册解读：UC3842参数和管脚说明
2024-05-22

5

产品中心

服务支持

精选活动

关于我们

帮助中心

71V3557SA85BQG8

71V3557SA85BQG8 技术参数

71V3557SA85BQG8 数据手册

与71V3557SA85BQG8相关器件

与71V3557SA85BQG8相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

71V3557SA85BQG8

71V3557SA85BQG8 技术参数

71V3557SA85BQG8 数据手册

与71V3557SA85BQG8相关器件

与71V3557SA85BQG8相关文章

您还可以找

您在本页遇到什么问题？