Datasheet > 71V3557SA85BQGI

71V3557SA85BQGI

更新时间： 2024-02-19 13:04:31

品牌	Logo	应用领域
艾迪悌 - IDT		时钟静态存储器内存集成电路
页数	文件大小	规格书
28页	523K
描述
Cache SRAM, 128KX36, 8.5ns, CMOS, PBGA165, 13 X 15 MM, PLASTIC, FBGA-165

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技术参数
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71V3557SA85BQGI 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	TBGA, BGA165,11X15,40
针数：	165	Reach Compliance Code：	unknown
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.53	最长访问时间：	8.5 ns
其他特性：	FLOW-THROUGH ARCHITECHTURE	备用内存宽度：	18
最大时钟频率 (fCLK)：	90 MHz	I/O 类型：	COMMON
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	15 mm	内存密度：	4718592 bit
内存集成电路类型：	CACHE SRAM	内存宽度：	36
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	131072 words
字数代码：	128000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	128KX36	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, THIN PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	电源：	3.3 V
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大待机电流：	0.045 A	最小待机电流：	3.14 V
子类别：	SRAMs	最大压摆率：	0.235 mA
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	13 mm
Base Number Matches：	1

71V3557SA85BQGI 数据手册

128K x 36, 256K x 18,

IDT71V3557S

IDT71V3559S

IDT71V3557SA

IDT71V3559SA

3.3V Synchronous ZBT™ SRAMs

3.3V I/O, Burst Counter,

Flow-Through Outputs

Features

it read or write.

◆

128K x 36, 256K x 18 memory configurations

Supports high performance system speed - 100 MHz

(7.5 ns Clock-to-Data Access)

The IDT71V3557/59 contain address, data-in and control signal

registers.Theoutputsareflow-through(nooutputdataregister).Output

enable is the only asynchronous signal and can be used to disable the

outputsatanygiventime.

A Clock Enable (CEN) pin allows operation of the IDT71V3557/59

to be suspended as long as necessary. All synchronous inputs are

ignored when (CEN) is high and the internal device registers will hold

their previous values.

Therearethreechipenablepins(CE1,CE2,CE2)thatallowtheuser

todeselectthedevicewhendesired.Ifanyoneofthesethreeisnotasserted

when ADV/LD is low, no new memory operation can be

initiated. However, any pending data transfers (reads or writes) will

be completed. The data bus will tri-state one cycle after chip is de-

selectedorawriteisinitiated.

The IDT71V3557/59 have an on-chip burst counter. In the burst

mode, the IDT71V3557/59 can provide four cycles of data for a single

address presented to the SRAM. The order of the burst sequence is

defined by the LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/LD signal is used to load a new

externaladdress(ADV/LD=LOW)orincrementtheinternalburstcounter

(ADV/LD = HIGH).

◆

ZBT^TMFeature - No dead cycles between write and read

cycles

Internally synchronized output buffer enable eliminates

the need to control OE

Single R/W (READ/WRITE) control pin

4-word burst capability (Interleaved or linear)

Individual byte write (BW¹- BW⁴) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%), 3.3V (±5%) I/O Supply (VDDQ)

Optional Boundary Scan JTAG Interface (IEEE 1149.1

complaint)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine

pitch ball grid array (fBGA)

◆

Description

TheIDT71V3557/59are3.3Vhigh-speed4,718,592-bit(4.5Mega-

bit)synchronous SRAMs organizedas 128Kx36/256Kx18. Theyare

designed to eliminate dead bus cycles when turning the bus around

between reads and writes, or writes and reads. Thus they have been

given the name ZBT^TM, or Zero Bus Turnaround.

The IDT71V3557/59 SRAMs utilize IDT's latest high-performance

CMOSprocessandarepackagedinaJEDECstandard14mmx20mm

100-pin thinplasticquadflatpack(TQFP)aswellasa119 ballgridarray

(BGA) and a 165 fine pitch ball grid array (fBGA).

AddressandcontrolsignalsareappliedtotheSRAMduringoneclock

cycle,andonthenextclockcycletheassociateddatacycleoccurs,be

PinDescriptionSummary

A0-A17

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE¹, CE2, CE²

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

BW¹, BW², BW³, BW⁴

CLK

ADV/LD

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

LBO

TMS

Synchronous

N/A

TDI

TCK

Te s t Cl o c k

TDO

Te s t Data Outp ut

Synchronous

Asynchronous

Synchronous

Static

JTAG Reset (Optional)

Sleep Mode

TRST

I/O0-I/O31, I/OP1-I/OP4

VDD, VDDQ

Data Input / Output

Core Power, I/O Power

Ground

Supply

VSS

Static

52 82 tb l 01

FEBRUARY 2009

DECEMBER 2005

DSC-5282/08

12 3 4 5 6 7...28

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与71V3557SA85BQGI相关器件

型号	品牌	描述	获取价格	数据表
71V3557SA85BQGI8	IDT	SRAM	获取价格
71V3557SA85BQI	IDT	ZBT SRAM, 128KX36, 8.5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165	获取价格
71V3557SA85BQI8	IDT	SRAM	获取价格
71V3557SA85PFGI	IDT	Cache SRAM, 128KX36, 8.5ns, CMOS, PQFP100, 14 X 20 MM, PLASTIC, TQFP-100	获取价格
71V3558	RENESAS	3.3V 256K x 18 ZBT Synchronous PipeLined SRAM w/3.3V I/O	获取价格
71V3558S100BGI	IDT	ZBT SRAM, 256KX18, 5ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, BGA-119	获取价格

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