IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration 256K x 18
Absolute Maximum Ratings (1)
Commercial &
Industrial Values
Symbol
Rating
Unit
(2 )
VTERM
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
NC
NC
NC
DDQ
V
SS
V
NC
NC
10
A
(3,6)
VTERM
Terminal Voltage with
Respect to GND
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-0 to +70
V
V
2
NC
NC
3
4
DDQ
V
V
5
(4,6)
76
75
74
73
SS
VTERM
Terminal Voltage with
Respect to GND
6
NC
7
P1
I/O
8
8
I/O
7
I/O
(5,6)
9
9
I/O
72
71
70
6
I/O
VTERM
Terminal Voltage with
Respect to GND
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
V
SS
V
V
DDQ
V
DDQ
5
69
68
67
66
10
I/O
I/O
11
Commercial
Operating Temperature
oC
oC
oC
oC
W
I/O
4
I/O
(1)
SS
V
SS
V
(7)
(1)
TA
VDD
(2)
VSS
65
64
DD
DD
V
SS/ZZ
V
3
I/O
2
I/O
V
Industrial
Operating Temperature
-40 to +85
(1,4)
SS
V
63
62
61
60
59
58
57
56
55
12
I/O
13
I/O
DDQ
DDQ
V
V
V
TBIAS
Temperature
Under Bias
-55 to +125
SS
14
V
I/O
SS
1
I/O
15
I/O
0
I/O
NC
NC
P2
I/O
Storage
Temperature
-55 to +125
TSTG
NC
SS
V
SS
V
V
,
54
53
DDQ
V
DDQ
PT
Power Dissipation
DC Output Current
2.0
50
NC
NC
NC
NC
NC
NC
52
51
IOUT
mA
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5282 tbl 06
5282 drw 02a
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
Top View
100TQFP
NOTES:
1. Pins14,64,and66donothavetobeconnecteddirectlytoVSSaslongastheinputvoltage
is < VIL.
2. Pin 16 does not have to be connected directly to VDD as long as the input voltage
is > VIH.
3. Pins 83 and 84 are reserved for future 8M and 16M respectively.
4. Pin 64 supports ZZ (sleep mode) for the latest die revisions.
7. TA is the "instant on" case temperature.
100TQFPCapacitance(1)
(TA = +25°C, F = 1.0MHZ)
119BGACapacitance(1)
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
(TA = +25°C, F = 1.0MHZ)
Symbol
CIN
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
5
7
pF
7
7
pF
CI/O
pF
5282 tbl 07
CI/O
pF
5282 tbl 07a
119BGACapacitance(1)
(TA = +25°C, F = 1.0MHZ)
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
TBD pF
CI/O
TBD pF
5282 tbl 07b
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.462
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