71V2556S100PFG8 PDF预览

71V2556S100PFG8

更新时间: 2025-09-21 19:36:11
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟存储
页数 文件大小 规格书
25页 270K
描述
存储容量(Mb):4.5Mb(128K x 36);内存数据长度(bit):128K ;字编码数(k):128K ;最大时钟频率(MHz):100 MHz;元器件封装:100-TQFP(14x14);

71V2556S100PFG8 数据手册

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71V2556S  
128K x 36  
71V2556SA  
3.3V Synchronous ZBT™ SRAMs  
2.5V I/O, Burst Counter  
Pipelined Outputs  
Features  
128K x 36 memory configurations  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)  
Optional - Boundary Scan JTAG Interface (IEEE 1149.1  
complaint)  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP) and 119 ball grid array (BGA)  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Supports high performance system speed - 166 MHz  
(3.5 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelined applications  
4-word burst capability (interleaved or linear)  
Green parts available, see ordering information  
FunctionalBlockDiagram  
LBO  
128Kx36 BIT  
MEMORY ARRAY  
Address A [0:16]  
D
D
Q
Q
Address  
CE1, CE2,  
CE2  
R/W  
Control  
CEN  
ADV/LD  
BWx  
DI  
DO  
D
Q
Control Logic  
Clk  
Mux  
Sel  
D
Clock  
Output Register  
Q
Gate  
OE  
,
4875 drw 01a  
TMS  
TDI  
TCK  
Data I/O [0:31],  
I/O P[1:4]  
JTAG  
(SA Version)  
TDO  
TRST  
(optional)  
ZBT and ZeroBus Turnaround are trademarks of Renesas and the architecture is supported by Micron Technology and Motorola Inc.  
1
Aug.20.20  

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