Datasheet > 71T75802200BGI8

71T75802200BGI8

更新时间： 2024-11-06 00:16:19

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
23页	1292K
描述
Synchronous ZBT SRAMs

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数据手册

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71T75802200BGI8 数据手册

512K x 36, 1M x 18

IDT71T75602

IDT71T75802

2.5V Synchronous ZBT™ SRAMs

2.5V I/O, Burst Counter

Pipelined Outputs

Description

Features

The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit

(18 Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead

bus cycles when turning the bus around between reads and writes, or

writesandreads. Thus, theyhavebeengiventhenameZBT^TM, orZero

Bus Turnaround.

•

512K x 36, 1M x 18 memory configurations

Supports high performance system speed - 200 MHz

(3.2 ns Clock-to-Data Access)

•

ZBT^TMFeature - No dead cycles between write and read

cycles

Address and control signals are applied to the SRAM during one

clockcycle, andtwocycleslatertheassociateddatacycleoccurs, beit

read or write.

Internally synchronized output buffer enable eliminates the

need to control OE

•

Single R/W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (BW1 - BW4) control (May tie active)

Three chip enables for simple depth expansion

2.5V power supply (±5%)

TheIDT71T75602/802containdataI/O,addressandcontrolsignal

registers.Outputenableistheonlyasynchronoussignalandcanbeused

todisabletheoutputsatanygiventime.

•

A Clock Enable CEN pin allows operation of the IDT71T75602/802

tobesuspendedaslongasnecessary.Allsynchronousinputsareignored

when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious

values.

2.5V I/O Supply (VDDQ)

There are three chip enable pins (CE1, CE2, CE2) that allow the

usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot

assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.

However,anypendingdatatransfers(readsorwrites)willbecompleted.

Power down controlled by ZZ input

Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)

Packaged in a JEDEC standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA)

Pin Description Summary

0-A19

Address Inputs

Input

Output

Input

I/O

Synchronous

Asynchronous

Synchronous

N/A

Chip Enables

CE1, CE

, CE

Output Enable

R/W

Read/Write Signal

Clock Enable

CEN

Individual Byte Write Selects

Clock

, BW

CLK

ADV/LD

LBO

TMS

TDI

Advance burst address / Load new address

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Synchronous

Static

N/A

TCK

Test Clock

N/A

TDO

TRST

Test Data Input

N/A

JTAG Reset (Optional)

Sleep Mode

Asynchronous

Synchronous

Static

I/O

-I/O31, I/OP1-I/OP4

Data Input / Output

Core Power, I/O Power

Ground

DD, VDDQ

Supply

Static

5313 tbl 01

APRIL 2012

DSC-5313/10

12 3 4 5 6 7...23

中文翻译

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