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71T75802S133BG8 PDF预览

71T75802S133BG8

更新时间: 2024-11-06 00:22:27
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
26页 260K
描述
2.5V Synchronous ZBT SRAMs I/O, Burst Counter Pipelined Outputs

71T75802S133BG8 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:PBGA
包装说明:BGA, BGA119,7X17,50针数:119
Reach Compliance Code:not_compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.14
最长访问时间:4.2 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
JESD-30 代码:R-PBGA-B119JESD-609代码:e0
长度:22 mm内存密度:18874368 bit
内存集成电路类型:ZBT SRAM内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:119字数:1048576 words
字数代码:1000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1MX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA119,7X17,50封装形状:RECTANGULAR
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:2.5 V
认证状态:Not Qualified座面最大高度:2.36 mm
最大待机电流:0.04 A最小待机电流:2.38 V
子类别:SRAMs最大压摆率:0.195 mA
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn63Pb37)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

71T75802S133BG8 数据手册

 浏览型号71T75802S133BG8的Datasheet PDF文件第2页浏览型号71T75802S133BG8的Datasheet PDF文件第3页浏览型号71T75802S133BG8的Datasheet PDF文件第4页浏览型号71T75802S133BG8的Datasheet PDF文件第5页浏览型号71T75802S133BG8的Datasheet PDF文件第6页浏览型号71T75802S133BG8的Datasheet PDF文件第7页 
512K x 36, 1M x 18  
IDT71T75602  
IDT71T75802  
2.5V Synchronous ZBT™ SRAMs  
2.5V I/O, Burst Counter  
Pipelined Outputs  
Features  
512K x 36, 1M x 18 memory configurations  
4-word burst capability (interleaved or linear)  
Supports high performance system speed - 200 MHz  
(3.2 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelinedapplications  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
2.5V power supply ( 5%)  
2.5V I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA)  
Green parts available, see Ordering Information  
Functional Block Diagram - 512K x 36  
LBO  
512Kx36 BIT  
MEMORY ARRAY  
Address A [0:18]  
D
D
Q
Q
Address  
CE1, CE2, CE2  
R/W  
CEN  
Control  
ADV/LD  
BWx  
DI DO  
D
Q
Control Logic  
Clk  
Mux  
Sel  
D
Clock  
Output Register  
Q
Gate  
OE  
TMS  
TDI  
TCK  
Data I/O [0:31],  
I/O P[1:4]  
JTAG  
TDO  
TRST  
5313 drw 01  
(optional)  
OCTOBER 2017  
1
©2017 Integrated Device Technology, Inc.  
DSC-5313/11  

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