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71T75602S166BGI8 PDF预览

71T75602S166BGI8

更新时间: 2024-12-02 00:22:27
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
26页 260K
描述
2.5V Synchronous ZBT SRAMs I/O, Burst Counter Pipelined Outputs

71T75602S166BGI8 数据手册

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512K x 36, 1M x 18  
IDT71T75602  
IDT71T75802  
2.5V Synchronous ZBT™ SRAMs  
2.5V I/O, Burst Counter  
Pipelined Outputs  
Features  
512K x 36, 1M x 18 memory configurations  
4-word burst capability (interleaved or linear)  
Supports high performance system speed - 200 MHz  
(3.2 ns Clock-to-Data Access)  
ZBTTM Feature - No dead cycles between write and read  
cycles  
Internally synchronized output buffer enable eliminates the  
need to control OE  
Single R/W (READ/WRITE) control pin  
Positive clock-edge triggered address, data, and control  
signal registers for fully pipelinedapplications  
Individual byte write (BW1 - BW4) control (May tie active)  
Three chip enables for simple depth expansion  
2.5V power supply ( 5%)  
2.5V I/O Supply (VDDQ)  
Power down controlled by ZZ input  
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)  
Packaged in a JEDEC standard 100-pin plastic thin quad  
flatpack (TQFP), 119 ball grid array (BGA)  
Green parts available, see Ordering Information  
Functional Block Diagram - 512K x 36  
LBO  
512Kx36 BIT  
MEMORY ARRAY  
Address A [0:18]  
D
D
Q
Q
Address  
CE1, CE2, CE2  
R/W  
CEN  
Control  
ADV/LD  
BWx  
DI DO  
D
Q
Control Logic  
Clk  
Mux  
Sel  
D
Clock  
Output Register  
Q
Gate  
OE  
TMS  
TDI  
TCK  
Data I/O [0:31],  
I/O P[1:4]  
JTAG  
TDO  
TRST  
5313 drw 01  
(optional)  
OCTOBER 2017  
1
©2017 Integrated Device Technology, Inc.  
DSC-5313/11  

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