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71T016SA12Y1 PDF预览

71T016SA12Y1

更新时间: 2023-02-26 14:15:22
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管
页数 文件大小 规格书
9页 137K
描述
Standard SRAM, 64KX16, 12ns, CMOS, PDSO44

71T016SA12Y1 数据手册

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IDT71T016SA, 2.5V CMOS Static RAM  
for Automotive Applications 1 Meg (64K x 16-Bit)  
Automotive Temperature Ranges  
AC Electrical Characteristics (VDD = Min. to Max., Automotive Temperature Ranges)  
71T016SA12  
71T016SA15  
71T016SA20  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
READ CYCLE  
____  
____  
____  
tRC  
Read Cycle Time  
12  
15  
20  
ns  
ns  
ns  
ns  
____  
____  
____  
tAA  
tACS  
Address Access Time  
12  
15  
20  
____  
____  
____  
Chip Select Access Time  
Chip Select Low to Output in Low-Z  
12  
15  
20  
____  
____  
____  
(1,2)  
4
5
5
tCLZ  
____  
____  
____  
(1,2)  
Chip Select High to Output in High-Z  
Output Enable Low to Output Valid  
Output Enable Low to Output in Low-Z  
1
1
3
ns  
ns  
ns  
tCHZ  
____  
____  
____  
tOE  
6
7
8
____  
____  
____  
(1,2)  
0
0
0
tOLZ  
____  
____  
____  
(1,2)  
Output Enable High to Output in High-Z  
Output Hold from Address Change  
Byte Enable Low to Output Valid  
Byte Enable Low to Output in Low-Z  
1
1
3
ns  
ns  
ns  
ns  
tOHZ  
tOH  
tBE  
4
4
4
____  
6
7
8
____  
____  
____  
(1,2)  
0
0
0
tBLZ  
____  
____  
____  
(1,2)  
Byte Enable High to Output in High-Z  
Chip Select Low to Power Up  
1
1
3
ns  
ns  
ns  
tBHZ  
____  
____  
____  
(3)  
0
0
0
tPU  
____  
____  
____  
(3)  
Chip Select High to Power Down  
12  
15  
20  
tPD  
WRITE CYCLE  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
tWC  
tAW  
tCW  
tBW  
tAS  
Write Cycle Time  
12  
8
8
8
0
0
8
6
0
15  
10  
10  
10  
0
20  
12  
12  
12  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address Valid to End of Write  
Chip Select Low to End of Write  
Byte Enable Low to End of Write  
Address Set-up Time  
tWR  
tWP  
tDW  
tDH  
Address Hold from End of Write  
Write Pulse Width  
0
0
10  
7
12  
9
Data Valid to End of Write  
Data Hold Time  
0
0
____  
____  
____  
(1,2)  
Write Enable High to Output in Low-Z  
3
3
3
tOW  
____  
____  
____  
(1,2)  
Write Enable Low to Output in High-Z  
4
4
6
ns  
tWHZ  
6473 tbl 10  
NOTES:  
1. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ, and tWHZ is less than tOW for any given device.  
2. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.  
3. This parameter is guaranteed by design and not production tested.  
Timing Waveform of Read Cycle No. 1(1,2,3)  
t
RC  
ADDRESS  
DATAOUT  
t
AA  
tOH  
DATAOUT VALID  
t
OH  
PREVIOUS DATAOUT VALID  
6473 drw 06  
NOTES:  
1. WE is HIGH for Read Cycle.  
2. Deviceiscontinuouslyselected,CSisLOW.  
3. OE, BHE, and BLE are LOW.  
6.42  
5

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