512K x 36, 1M x 18
IDT71T75602
IDT71T75802
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
Description
Features
The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit
(18 Megabit)synchronousSRAMs.Theyaredesignedtoeliminatedead
bus cycles when turning the bus around between reads and writes, or
writesandreads. Thus, theyhavebeengiventhenameZBTTM, orZero
Bus Turnaround.
•
•
512K x 36, 1M x 18 memory configurations
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
•
•
ZBTTM Feature - No dead cycles between write and read
cycles
Address and control signals are applied to the SRAM during one
clockcycle, andtwocycleslatertheassociateddatacycleoccurs, beit
read or write.
Internally synchronized output buffer enable eliminates the
need to control OE
•
•
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
2.5V power supply (±5%)
TheIDT71T75602/802containdataI/O,addressandcontrolsignal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
•
•
•
•
•
•
•
•
A Clock Enable CEN pin allows operation of the IDT71T75602/802
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
2.5V I/O Supply (VDDQ)
There are three chip enable pins (CE1, CE2, CE2) that allow the
usertodeselectthedevicewhendesired.Ifanyoneofthesethreeisnot
assertedwhenADV/LDislow,nonewmemoryoperationcanbeinitiated.
However,anypendingdatatransfers(readsorwrites)willbecompleted.
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Pin Description Summary
A
0-A19
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE1, CE
2
, CE
2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW
1
, BW
2
, BW
3
, BW
4
CLK
ADV/LD
LBO
TMS
TDI
Advance burst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Synchronous
Static
N/A
N/A
TCK
Test Clock
N/A
TDO
TRST
ZZ
Test Data Input
N/A
JTAG Reset (Optional)
Sleep Mode
Asynchronous
Synchronous
Synchronous
Static
I/O
0
-I/O31, I/OP1-I/OP4
Data Input / Output
Core Power, I/O Power
Ground
V
V
DD, VDDQ
SS
Supply
Supply
Static
5313 tbl 01
APRIL 2012
1
©2012IntegratedDeviceTechnology,Inc.
DSC-5313/10
5秒后页面跳转
STM32H743技术深度剖析与应用案例探索
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
74HC14芯片资料介绍：性能特性分析、引脚介绍
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
数据手册
如果您发现信息不准确，
