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71421LA20TFG8 PDF预览

71421LA20TFG8

更新时间: 2024-09-29 20:01:35
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
18页 145K
描述
Multi-Port SRAM, 2KX8, 20ns, CMOS, PQFP64

71421LA20TFG8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:QFP, QFP64,.47SQ,20
Reach Compliance Code:compliant风险等级:5.28
最长访问时间:20 nsI/O 类型:COMMON
JESD-30 代码:S-PQFP-G64JESD-609代码:e3
内存密度:16384 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端口数量:2
端子数量:64字数:2048 words
字数代码:2000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP64,.47SQ,20封装形状:SQUARE
封装形式:FLATPACK并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified最大待机电流:0.0015 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.2 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
Base Number Matches:1

71421LA20TFG8 数据手册

 浏览型号71421LA20TFG8的Datasheet PDF文件第2页浏览型号71421LA20TFG8的Datasheet PDF文件第3页浏览型号71421LA20TFG8的Datasheet PDF文件第4页浏览型号71421LA20TFG8的Datasheet PDF文件第5页浏览型号71421LA20TFG8的Datasheet PDF文件第6页浏览型号71421LA20TFG8的Datasheet PDF文件第7页 
IDT71321SA/LA  
IDT71421SA/LA  
HIGH SPEED  
2K X 8 DUAL-PORT  
STATIC RAM WITH INTERRUPTS  
Features  
MASTER IDT71321 easily expands data bus width to 16-or-  
more-bits using SLAVE IDT71421  
High-speed access  
– Commercial: 20/25/35/55ns (max.)  
Industrial: 25/55ns (max.)  
Low-power operation  
On-chip port arbitration logic (IDT71321 only)  
BUSY output flag on IDT71321; BUSY input on IDT71421  
Fully asynchronous operation from either port  
Battery backup operation – 2V data retention (LA only)  
TTL-compatible, single 5V ±10% power supply  
Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
IDT71321/IDT71421SA  
Active: 325mW (typ.)  
Standby: 5mW (typ.)  
IDT71321/421LA  
Active: 325mW (typ.)  
Standby: 1mW (typ.)  
Two INT flags for port-to-port communications  
Green parts available, see ordering information  
FunctionalBlockDiagram  
OER  
OEL  
CE  
R/W  
L
CE  
R/W  
R
L
R
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
I/O  
Control  
Control  
BUSY (1,2)  
L
(1,2)  
R
BUSY  
A
10L  
A
10R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
11  
11  
ARBITRATION  
and  
INTERRUPT  
LOGIC  
CE  
OE  
L
L
CE  
OE  
R/W  
R
R
R
R/W  
L
(2)  
R
(2)  
L
INT  
INT  
2691 drw 01  
NOTES:  
1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270.  
IDT71421 (SLAVE): BUSY is input.  
2. Open drain output: requires pullup resistor of 270.  
AUGUST 2006  
1
DSC-2691/12  
©2006IntegratedDeviceTechnology,Inc.  

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