Datasheet > 71421LA20PPGI

71421LA20PPGI

更新时间： 2024-11-17 00:22:23

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
18页	184K
描述
HIGH SPEED 2K X 8 DUAL-PORT STATIC RAM

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中文翻译

获取价格

数据手册

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71421LA20PPGI 数据手册

HIGH SPEED

IDT71321SA/LA

IDT71421SA/LA

2K X 8 DUAL-PORT

STATIC RAM

WITH INTERRUPTS

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features

High-speed access

◆

MASTER IDT71321 easily expands data bus width to 16-or-

◆

more-bits using SLAVE IDT71421

◆

– Commercial: 20/25/35/55ns (max.)

– Industrial: 25/55ns (max.)

Low-power operation

On-chip port arbitration logic (IDT71321 only)

BUSY output flag on IDT71321; BUSY input on IDT71421

Fully asynchronous operation from either port

Battery backup operation – 2V data retention (LA only)

TTL-compatible, single 5V 10% power supply

Available in 52-Pin PLCC, 52-Pin STQFP, 64-Pin TQFP, and

64-Pin STQFP

◆

– IDT71321/IDT71421SA

— Active: 325mW (typ.)

— Standby: 5mW (typ.)

– IDT71321/421LA

◆

— Active: 325mW (typ.)

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

— Standby: 1mW (typ.)

◆

Two INT flags for port-to-port communications

Green parts available, see ordering information

Functional Block Diagram

CER

R/W

R/WR

I/O0L- I/O7L

I/O0R-I/O7R

I/O

Control

BUSY ^(1,2)

(1,2)

BUSY

10L

10R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A0R

ARBITRATION

and

INTERRUPT

LOGIC

R/W

(2)

INT

2691 drw 01

NOTES:

1. IDT71321(MASTER):BUSYisopendrainoutputandrequirespullupresistorof270Ω.

IDT71421 (SLAVE): BUSY is input.

2. Open drain output: requires pullup resistor of 270Ω.

FEBRUARY 2018

DSC-2691/16

12 3 4 5 6 7...18

中文翻译

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