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7140LA55PI PDF预览

7140LA55PI

更新时间: 2024-11-23 14:46:55
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
19页 153K
描述
Dual-Port SRAM, 1KX8, 55ns, CMOS, PDIP48, PLASTIC, DIP-48

7140LA55PI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP48,.6针数:48
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.04
最长访问时间:55 nsI/O 类型:COMMON
JESD-30 代码:R-PDIP-T48JESD-609代码:e0
长度:61.849 mm内存密度:8192 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:8
功能数量:1端口数量:2
端子数量:48字数:1024 words
字数代码:1000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:1KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP48,.6封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):225电源:5 V
认证状态:Not Qualified座面最大高度:5.08 mm
最大待机电流:0.004 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.14 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn85Pb15)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:15.24 mm
Base Number Matches:1

7140LA55PI 数据手册

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IDT7130SA/LA  
IDT7140SA/LA  
HIGH SPEED  
1K X 8 DUAL-PORT  
STATIC SRAM  
Features  
On-chip port arbitration logic (IDT7130 Only)  
High-speed access  
BUSY output flag on IDT7130; BUSY input on IDT7140  
INT flag for port-to-port communication  
– Commercial: 20/25/35/55/100ns (max.)  
Industrial: 25/55/100ns (max.)  
Military: 25/35/55/100ns (max.)  
Fully asynchronous operation from either port  
Battery backup operation–2V data retention (LA only)  
TTL-compatible, single 5V ±10% power supply  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Low-power operation  
IDT7130/IDT7140SA  
Active: 550mW (typ.)  
Standby: 5mW (typ.)  
IDT7130/IDT7140LA  
Active: 550mW (typ.)  
Standby: 1mW (typ.)  
Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin  
PLCC, and 64-pin STQFP and TQFP  
MASTER IDT7130 easily expands data bus width to 16-or-  
more-bits using SLAVE IDT7140  
Functional Block Diagram  
OER  
OEL  
CE  
R/W  
L
CE  
R/W  
R
L
R
,
I/O0L- I/O7L  
I/O0R-I/O7R  
(1,2)  
I/O  
Control  
I/O  
Control  
(1,2)  
BUSY  
L
BUSYR  
A
9L  
0L  
A
9R  
0R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
A
10  
10  
ARBITRATION  
and  
INTERRUPT  
LOGIC  
CE  
L
CE  
OE  
R/W  
R
R
OEL  
L
R
R/W  
(2)  
(2)  
INT  
R
INTL  
2689 drw 01  
NOTES:  
1. IDT7130 (MASTER): BUSY is open drain output and requires pullup resistor.  
IDT7140 (SLAVE): BUSY is input.  
2. Open drain output: requires pullup resistor.  
JANUARY 2002  
1
DSC-2689/11  
©2002IntegratedDeviceTechnology,Inc.  

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