IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
7133X20
7143X20
7133X25
7143X25
7133X35
7143X35
Com'l Only
Com'l, Ind
& Military
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
Write Cycle Time(3)
20
15
15
0
25
20
20
0
35
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
t
t
t
15
0
20
0
25
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
15
15
20
____
____
____
t
12
15
20
____
____
____
t
0
0
0
(1,2)
____
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1, 2,4)
12
15
20
____
____
____
t
0
0
0
ns
2746 tbl 11a
7133X45
7133X55
7133X70/90
7143X45
Com'l &
Military
7143X55
Com'l, Ind
& Military
7143X70/90
Com'l &
Military
Symbol
WRITE CYCLE
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
Write Cycle Time(3)
45
30
30
0
55
40
40
0
70/90
50/50
50/50
0/0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
t
t
t
30
0
40
0
50/50
0/0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
20
25
30/30
____
____
____
t
20
20
25/25
____
____
____
t
5
5
5/5
(1,2)
____
____
____
t
Write Enable to Output in High-Z
20
20
25/25
____
____
____
t
Output Active from End-of-Write(1, 2,4)
5
5
5/5
ns
2746 tbl 11b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage from the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but not production tested.
3. For MASTER/SLAVE combination, tWC = tBAA + tWR + tWP, since R/W = VIL must occur after tBAA.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operation conditions. Although tDH and tOW values will very over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (SA or LA).
9
6.42