5秒后页面跳转
捷配首页

Datasheet > 7133SA70PF
7133SA70PF PDF预览

7133SA70PF

更新时间： 2023-02-26 14:12:59
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器
页数 文件大小 规格书
16页 137K
描述
Dual-Port SRAM, 2KX16, 70ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

阅读下载

获取价格

7133SA70PF 数据手册

 浏览型号7133SA70PF的Datasheet PDF文件第7页浏览型号7133SA70PF的Datasheet PDF文件第8页浏览型号7133SA70PF的Datasheet PDF文件第9页浏览型号7133SA70PF的Datasheet PDF文件第11页浏览型号7133SA70PF的Datasheet PDF文件第12页浏览型号7133SA70PF的Datasheet PDF文件第13页 
IDT7133SA/LA,IDT7143SA/LA  
High-Speed 2K x 16 Dual-Port RAM  
Military, Industrial and Commercial Temperature Ranges  
AC Electrical Characteristics Over the  
OperatingTemperatureandSupplyVoltage(6)  
7133X20  
7133X25  
7143X25  
Com'l, Ind  
& Military  
7133X35  
7143X35  
Com'l, Ind  
& Military  
7143X20  
Com'l Only  
Symbol  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
BUSY TIMING (For MASTER 71V33)  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
t
BAA  
BDA  
BAC  
BDC  
WDD  
DDD  
BDD  
APS  
WH  
20  
20  
20  
17  
40  
30  
20  
20  
20  
20  
50  
35  
30  
30  
25  
25  
60  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
BUSY Access Time from Address  
BUSY Disable Time from Address  
t
t
BUSY Access Time from Chip Enable  
BUSY Disable Time from Chip Enable  
t
(1)  
t
Write Pulse to Data Delay  
t
Write Data Valid to Read Data Delay(1)  
BUSY Disable to Valid Data(2)  
Arbitration Priority Set-up Time(3)  
Write Hold After BUSY(5)  
t
25  
30  
35  
____  
____  
____  
t
5
5
5
____  
____  
____  
t
20  
20  
25  
BUSY INPUT TIMING (For SLAVE 71V43)  
____  
____  
____  
____  
____  
____  
BUSY Input to Write(4)  
t
WB  
WH  
WDD  
DDD  
0
0
0
ns  
ns  
ns  
t
Write Hold After BUSY(5)  
20  
20  
25  
(1)  
____  
____  
____  
t
Write Pulse to Data Delay  
40  
30  
50  
35  
60  
45  
Write Data Valid to Read Data Delay(1)  
ns  
____  
____  
____  
t
2746 tbl 12a  
7133X45  
7133X55  
7143X55  
Com'l, Ind  
& Military  
7133X70/90  
7143X45  
Com'l &  
Military  
7143X70/90  
Com'l &  
Military  
Symbol  
BUSY TIMING (For MASTER 71V33)  
Parameter  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
____  
t
BAA  
BDA  
BAC  
BDC  
WDD  
DDD  
BDD  
APS  
WH  
40  
40  
30  
25  
80  
55  
40  
40  
35  
30  
80  
55  
45/45  
45/45  
35/35  
30/30  
90/90  
70/70  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
BUSY Access Time from Address  
BUSY Disable Time from Address  
t
t
BUSY Access Time from Chip Enable  
BUSY Disable Time from Chip Enable  
t
(1)  
t
Write Pulse to Data Delay  
t
Write Data Valid to Read Data Delay(1)  
BUSY Disable to Valid Data(2)  
Arbitration Priority Set-up Time(3)  
Write Hold After BUSY(5)  
t
40  
40  
40/40  
____  
____  
____  
t
5
5
5/5  
____  
____  
____  
t
30  
30  
30/30  
BUSY INPUT TIMING (For SLAVE 71V43)  
____  
____  
____  
____  
____  
____  
BUSY Input to Write(4)  
Write Hold After BUSY(5)  
t
WB  
WH  
WDD  
DDD  
0
0
0/0  
ns  
ns  
ns  
t
30  
30  
30/30  
(1)  
____  
____  
____  
t
Write Pulse to Data Delay  
80  
55  
80  
55  
90/90  
70/70  
Write Data Valid to Read Data Delay(1)  
ns  
____  
____  
____  
t
2746 tbl 12b  
NOTES:  
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and Busy".  
2. tBDD is calculated parameter and is greater of 0, tWDD - tWP (actual) or tDDD - tDW (actual).  
3. To ensure that the earlier of the two ports wins.  
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".  
5. To ensure that a write cycle is completed on port "B" after contention on port "A".  
6. 'X' in part number indicates power rating (SA or LA).  
6.42  
10  
1...78910111213...16

下载PDF

与7133SA70PF相关器件

型号 品牌 描述 获取价格 数据表
7133SA90GG IDT Dual-Port SRAM, 2KX16, 90ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, GREEN, C

获取价格
7133SA90GG8 IDT Dual-Port SRAM, 2KX16, 90ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, GREEN, C

获取价格
7133SA90JB IDT Dual-Port SRAM, 2KX16, 90ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC,

获取价格
7133SA90PF IDT Dual-Port SRAM, 2KX16, 90ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

获取价格
7133SA90PFB IDT Dual-Port SRAM, 2KX16, 90ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100

获取价格
7133-V MOLEX Barrier Strip Terminal Block, 25A, 1 Row(s), 1 Deck(s)

获取价格

与7133SA70PF相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证