Datasheet > 71321SA25JGI8

71321SA25JGI8

更新时间： 2024-11-16 21:05:31

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
18页	145K
描述
Multi-Port SRAM, 2KX8, 25ns, CMOS, PQCC52

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中文翻译

获取价格

技术参数
数据手册

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71321SA25JGI8 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	包装说明：	QCCJ, LDCC52,.8SQ
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.41	风险等级：	5.26
Is Samacsys：	N	Base Number Matches：	1

71321SA25JGI8 数据手册

IDT71321SA/LA

IDT71421SA/LA

HIGH SPEED

2K X 8 DUAL-PORT

STATIC RAM WITH INTERRUPTS

Features

◆

MASTER IDT71321 easily expands data bus width to 16-or-

more-bits using SLAVE IDT71421

High-speed access

– Commercial: 20/25/35/55ns (max.)

– Industrial: 25/55ns (max.)

Low-power operation

◆

On-chip port arbitration logic (IDT71321 only)

BUSY output flag on IDT71321; BUSY input on IDT71421

Fully asynchronous operation from either port

Battery backup operation – 2V data retention (LA only)

TTL-compatible, single 5V ±10% power supply

Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

– IDT71321/IDT71421SA

— Active: 325mW (typ.)

— Standby: 5mW (typ.)

– IDT71321/421LA

— Active: 325mW (typ.)

— Standby: 1mW (typ.)

Two INT flags for port-to-port communications

◆

Green parts available, see ordering information

FunctionalBlockDiagram

OER

OEL

R/W

I/O0L- I/O7L

I/O0R-I/O7R

I/O

Control

BUSY ^(1,2)

(1,2)

BUSY

10L

10R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

ARBITRATION

and

INTERRUPT

LOGIC

R/W

(2)

INT

2691 drw 01

NOTES:

1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω.

IDT71421 (SLAVE): BUSY is input.

2. Open drain output: requires pullup resistor of 270Ω.

AUGUST 2006

DSC-2691/12

12 3 4 5 6 7...18

中文翻译

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