Datasheet > 71321SA25TFG9

71321SA25TFG9

更新时间： 2024-11-17 10:40:07

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
17页	161K
描述
Dual-Port SRAM, 2KX8, 25ns, CMOS, PQFP64, STQFP-64

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中文翻译

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数据手册

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71321SA25TFG9 数据手册

IDT71321SA/LA

IDT71421SA/LA

HIGH SPEED

2K X 8 DUAL-PORT

STATIC RAM WITH INTERRUPTS

Features

◆

MASTER IDT71321 easily expands data bus width to 16-or-

more-bits using SLAVE IDT71421

High-speed access

– Commercial: 20/25/35/55ns (max.)

– Industrial: 55ns (max.)

Low-power operation

◆

On-chip port arbitration logic (IDT71321 only)

BUSY output flag on IDT71321; BUSY input on IDT71421

Fully asynchronous operation from either port

Battery backup operation – 2V data retention (LA only)

TTL-compatible, single 5V ±10% power supply

Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

◆

– IDT71321/IDT71421SA

— Active: 325mW (typ.)

— Standby: 5mW (typ.)

– IDT71321/421LA

— Active: 325mW (typ.)

— Standby: 1mW (typ.)

Two INT flags for port-to-port communications

◆

FunctionalBlockDiagram

OER

OE_L

CEL

R/WL

CER

R/WR

I/O0L- I/O7L

I/O0R-I/O7R

I/O

Control

I/O

Control

(1,2)

BUSYL

(1,2)

BUSYR

A10L

A0L

A10R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A0R

ARBITRATION

and

INTERRUPT

LOGIC

CEL

OEL

CER

OER

R/WR

R/WL

(2)

INT_R

(2)

INTL

2691 drw 01

NOTES:

1. IDT71321 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω.

IDT71421 (SLAVE): BUSY is input.

2. Open drain output: requires pullup resistor of 270Ω.

MARCH 1999

DSC-2691/8

12 3 4 5 6 7...17

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