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71321LA55PPGI8 PDF预览

71321LA55PPGI8

更新时间: 2024-11-05 00:22:11
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
18页 184K
描述
HIGH SPEED 2K X 8 DUAL-PORT STATIC RAM

71321LA55PPGI8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TQFP
包装说明:QFP,针数:52
Reach Compliance Code:compliant风险等级:5.62
Samacsys Description:TQFP 10MM X10MM X 1.4MM最长访问时间:55 ns
JESD-30 代码:S-PQFP-G52JESD-609代码:e3
内存密度:16384 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:52
字数:2048 words字数代码:2000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:2KX8
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL峰值回流温度(摄氏度):260
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin (Sn)端子形式:GULL WING
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

71321LA55PPGI8 数据手册

 浏览型号71321LA55PPGI8的Datasheet PDF文件第2页浏览型号71321LA55PPGI8的Datasheet PDF文件第3页浏览型号71321LA55PPGI8的Datasheet PDF文件第4页浏览型号71321LA55PPGI8的Datasheet PDF文件第5页浏览型号71321LA55PPGI8的Datasheet PDF文件第6页浏览型号71321LA55PPGI8的Datasheet PDF文件第7页 
HIGH SPEED  
IDT71321SA/LA  
IDT71421SA/LA  
2K X 8 DUAL-PORT  
STATIC RAM  
WITH INTERRUPTS  
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018  
Features  
High-speed access  
MASTER IDT71321 easily expands data bus width to 16-or-  
more-bits using SLAVE IDT71421  
– Commercial: 20/25/35/55ns (max.)  
– Industrial: 25/55ns (max.)  
Low-power operation  
On-chip port arbitration logic (IDT71321 only)  
BUSY output flag on IDT71321; BUSY input on IDT71421  
Fully asynchronous operation from either port  
Battery backup operation – 2V data retention (LA only)  
TTL-compatible, single 5V 10% power supply  
Available in 52-Pin PLCC, 52-Pin STQFP, 64-Pin TQFP, and  
64-Pin STQFP  
– IDT71321/IDT71421SA  
Active: 325mW (typ.)  
Standby: 5mW (typ.)  
– IDT71321/421LA  
Active: 325mW (typ.)  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
Standby: 1mW (typ.)  
Two INT flags for port-to-port communications  
Green parts available, see ordering information  
Functional Block Diagram  
OE  
R
OE  
L
L
CE  
CER  
R/W  
L
R/WR  
I/O0L- I/O7L  
I/O0R-I/O7R  
I/O  
I/O  
Control  
Control  
BUSY (1,2)  
L
(1,2)  
R
BUSY  
A
10L  
A
10R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A0R  
11  
11  
ARBITRATION  
and  
INTERRUPT  
LOGIC  
CE  
L
L
CE  
OE  
R/W  
R
R
OE  
R
R/W  
L
(2)  
R
(2)  
L
INT  
INT  
2691 drw 01  
NOTES:  
1. IDT71321(MASTER):BUSYisopendrainoutputandrequirespullupresistorof270.  
IDT71421 (SLAVE): BUSY is input.  
2. Open drain output: requires pullup resistor of 270.  
FEBRUARY 2018  
1
©2018 Integrated Device Technology, Inc.  
DSC-2691/16  

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