5秒后页面跳转
70V9179L12PFG PDF预览

70V9179L12PFG

更新时间: 2024-02-27 10:55:36
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
17页 297K
描述
Dual-Port SRAM

70V9179L12PFG 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:QFP,Reach Compliance Code:compliant
风险等级:5.77最长访问时间:12 ns
JESD-30 代码:S-PQFP-G100内存密度:294912 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:9
功能数量:1端子数量:100
字数:32768 words字数代码:32000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32KX9
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIEDBase Number Matches:1

70V9179L12PFG 数据手册

 浏览型号70V9179L12PFG的Datasheet PDF文件第2页浏览型号70V9179L12PFG的Datasheet PDF文件第3页浏览型号70V9179L12PFG的Datasheet PDF文件第4页浏览型号70V9179L12PFG的Datasheet PDF文件第6页浏览型号70V9179L12PFG的Datasheet PDF文件第7页浏览型号70V9179L12PFG的Datasheet PDF文件第8页 
IDT70V9179L  
High-Speed 32K x 9 Dual-Port Synchronous Pipelined Static RAM  
Industrial and Commercial Temperature Ranges  
DC Electrical Characteristics Over the Operating  
Temperature Supply Voltage Range(3) (VDD = 3.3V ± 0.3V)  
70V9179L7  
Com'l Only  
70V9179L9  
Com'l & Ind  
70V9179L12  
Com'l Only  
Symbol  
Parameter  
Test Condition  
= VIL  
Version  
COM'L  
Typ.(4)  
Max.  
Typ.(4)  
Max.  
260  
280  
100  
120  
Typ.(4)  
Max.  
Unit  
ICC  
Dynamic Operating  
Current (Both  
Ports Active)  
mA  
L
L
L
L
200  
310  
180  
180  
50  
150  
230  
CE  
L
and CE  
R
,
Outputs Disabled,  
(1)  
____  
____  
____  
____  
IND  
f = fMAX  
ISB1  
Standby Current  
(Both Ports - TTL  
Level Inputs)  
mA  
mA  
COM'L  
IND  
65  
130  
40  
80  
CEL  
= CER = VIH  
(1)  
____  
____  
____  
____  
50  
f = fMAX  
ISB2  
Standby  
Current (One  
Port - TTL  
CE"A" = VIL and  
COM'L  
IND  
L
L
L
L
140  
245  
110  
110  
0.4  
0.4  
190  
205  
3
100  
175  
(5)  
CE"B" = VIH  
Active Port Outputs  
Disabled, f=fMAX  
____  
____  
____  
____  
(1)  
Level Inputs)  
ISB3  
Full Standby  
Current (Both  
Ports - CMOS  
Level Inputs)  
Both Ports CE  
L
and  
mA  
mA  
COM'L  
IND  
0.4  
3
0.4  
3
CE  
R
> VDD - 0.2V,  
V
V
IN > VDD - 0.2V or  
____  
____  
____  
____  
IN < 0.2V, f = 0(2)  
6
ISB4  
Full Standby  
Current (One  
Port - CMOS  
Level Inputs)  
CE"A" < 0.2V and  
COM'L  
IND  
L
L
130  
235  
100  
100  
180  
195  
90  
165  
CE"B" > VDD - 0.2V(5)  
V
V
IN > VDD - 0.2V or  
IN < 0.2V, Active Port,  
Outputs Disabled, f = fMAX  
____  
____  
____  
____  
(1)  
4860 tbl 09_79  
NOTES:  
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input  
levels of GND to 3V.  
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.  
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".  
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ).  
5. CEX = VIL means CE0X = VIL and CE1X = VIH  
CEX = VIH means CE0X = VIH or CE1X = VIL  
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V  
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V  
"X" represents "L" for left port or "R" for right port.  
6.42  
5

与70V9179L12PFG相关器件

型号 品牌 描述 获取价格 数据表
70V9179L12PFG8 IDT Dual-Port SRAM

获取价格

70V9179L12PFGI IDT HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

获取价格

70V9179L12PFGI8 IDT HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

获取价格

70V9179L6PF IDT Dual-Port SRAM, 32KX9, 6.5ns, CMOS, PQFP100, 14 X 14 MM, 1.4 MM HEIGHT, TQFP-100

获取价格

70V9179L7PFG IDT HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

获取价格

70V9179L7PFG8 IDT Dual-Port SRAM, 32KX9, 18ns, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, GREEN, TQFP-100

获取价格