Datasheet > 70V9179L12PFGI

70V9179L12PFGI

更新时间： 2024-02-22 23:16:58

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
17页	204K
描述
HIGH-SPEED 3.3V SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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数据手册

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70V9179L12PFGI 数据手册

HIGH-SPEED 3.3V 32K x 9

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

IDT70V9179L

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features:

◆

Counter enable and reset features

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

– Commercial:7.5/9/12ns(max.)

– Industrial: 9ns (max.)

Full synchronous operation on both ports

– 4ns setup to clock and 0ns hold on all control, data, and

addressinputs

– Data input, address, and control registers

– Fast 7.5ns clock to data out in the Pipelined output mode

– Self-timedwriteallowsfastcycletime

◆

Low-power operation

– IDT70V9179L

– 12ns cycle time, 83MHz operation in Pipelined output mode

LVTTL- compatible, single 3.3V ( 0.3V) power supply

Industrial temperature range (–40°C to +85°C) is

available for selected speeds

Available in a 100-pin Thin Quad Flatpack (TQFP)

Green parts available, see ordering information

Active:500mW(typ.)

Standby: 1.5mW (typ.)

Flow-Through or Pipelined output mode on either port via

the FT/PIPE pins

Dual chip enables allow for depth expansion without

additional logic

◆

Functional Block Diagram

R/W

CE0L

CE1L

CE0R

CE1R

0/1

FT/PIPE

I/O0L - I/O8L

I/O0R - I/O8R

I/O

Control

I/O

Control

A14L

A14R

Counter/

Address

Reg.

Counter/

Address

Reg.

MEMORY

ARRAY

CLK

ADS

CNTEN

CNTRST

CLK

ADS

CNTEN

CNTRST

4860 drw 01

FEBRUARY 2018

DSC-4860/6

12 3 4 5 6 7...17

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