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70V7599S133BFG8 PDF预览

70V7599S133BFG8

更新时间: 2024-02-07 14:48:31
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
22页 748K
描述
Dual-Port SRAM, 128KX36, 4.2ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, GREEN, FPBGA-208

70V7599S133BFG8 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:BGA, BGA208,17X17,32Reach Compliance Code:compliant
HTS代码:8542.32.00.41风险等级:5.74
最长访问时间:4.2 ns其他特性:PIPELINED OR FLOW THROUGH ARCHITECTURE
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
JESD-30 代码:S-PBGA-B208内存密度:4718592 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:36
功能数量:1端口数量:2
端子数量:208字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA208,17X17,32封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
电源:2.5/3.3,3.3 V认证状态:Not Qualified
最大待机电流:0.03 A最小待机电流:3.15 V
子类别:SRAMs最大压摆率:0.645 mA
最大供电电压 (Vsup):3.45 V最小供电电压 (Vsup):3.15 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOMBase Number Matches:1

70V7599S133BFG8 数据手册

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IDT70V7599S  
High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM  
Industrial and Commercial Temperature Ranges  
Identification Register Definitions  
Instruction Field  
Value  
0x0  
Description  
Revision Number (31:28)  
Reserved for version number  
IDT Device ID (27:12)  
0x308  
0x33  
1
Defines IDT part number  
IDT JEDEC ID (11:1)  
Allows unique identification of device vendor as IDT  
Indicates the presence of an ID register  
ID Register Indicator Bit (Bit 0)  
5626 tbl 13  
ScanRegisterSizes  
Register Name  
Bit Size  
Instruction (IR)  
4
1
Bypass (BYR)  
Identification (IDR)  
32  
Boundary Scan (BSR)  
Note (3)  
5626 tbl 14  
SystemInterfaceParameters  
Instruction  
Code  
Description  
EXTEST  
0000  
Forces contents of the boundary scan cells onto the device outputs(1).  
Places the boundary scan register (BSR) between TDI and TDO.  
BYPASS  
IDCODE  
1111  
Places the by pass registe r (BYR) between TDI and TDO.  
0010  
Loads the ID register (IDR) with the vendor ID code and places the  
register between TDI and TDO.  
0100  
Places the bypass register (BYR) between TDI and TDO. Forces all  
device output drivers to a High-Z state.  
HIGHZ  
Uses BYR. Forces contents of the boundary scan cells onto the device  
outputs. Places the bypass register (BYR) between TDI and TDO.  
CLAMP  
0011  
0001  
SAMPLE/PRELOAD  
Places the boundary scan register (BSR) between TDI and TDO.  
SAMPLE allows data from device inputs(2) and outputs(1) to be captured  
in the boundary scan cells and shifted serially through TDO. PRELOAD  
allows data to be input serially into the boundary scan cells via the TDI.  
RESERVED  
All other codes  
Several combinations are reserved. Do not use codes other than those  
identified above.  
5626 tbl 15  
NOTES:  
1. Device outputs = All device outputs except TDO.  
2. Device inputs = All device inputs except TDI, TMS, TRST, and TCK.  
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local  
IDT sales representative.  
6.42  
21  

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