Datasheet > 70V7519S166BFGI8

70V7519S166BFGI8

更新时间： 2022-12-29 21:38:42

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	756K
描述
HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM

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IDT70V7519S

High-Speed 256K x 36 Synchronous Bank-Switchable Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)⁽²⁾

CYC1

tCH1

tCL1

CLK

CE0

tSC

tHC

CE1

tSB

tHB

BEn

tSW tHW

R/W

tSW tHW

(3)

An + 4

An + 3

An +1

An + 2

ADDRESS

tSA

tHA

tHD

DATAIN

Dn + 2

CD1

tCD1

(1)

Qn + 3

READ

Qn + 1

DATAOUT

tDC

tCKLZ

tDC

CKHZ

NOP⁽⁴⁾

READ

WRITE

5618 drw 14

TimingWaveformof Flow-ThroughRead-to-Write-to-Read(OEControlled)⁽²⁾

CYC1

tCH1

tCL1

CLK

tSC

tHC

tSB

tHB

BEn

tSW tHW

R/W

(3)

An + 5

An + 4

An +1

An + 2

An + 3

Dn + 3

ADDRESS

DATAIN

tHA

SD tHD

Dn + 2

tDC

tCD1

CD1

(1)

Qn + 4

DATAOUT

tCKLZ

tDC

tOHZ

READ

WRITE

READ

5618 drw 15

NOTES:

1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.

2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.

3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for

reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

6.42

1...13 14 151617 18 19...22

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与70V7519S166BFGI8相关器件

型号	品牌	获取价格	描述	数据表
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70V7519S200BCG	IDT	获取价格	CABGA-256, Tray
70V7519S200BCG8	IDT	获取价格	HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM