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70V7319S200BF PDF预览

70V7319S200BF

更新时间： 2024-01-04 23:19:01
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
22页 222K
描述
Dual-Port SRAM, 256KX18, 10ns, PBGA208, FBGA-208

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70V7319S200BF 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：BGA
包装说明：TFBGA,针数：208
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.8
最长访问时间：10 ns其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码：S-PBGA-B208JESD-609代码：e0
长度：15 mm内存密度：4718592 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：18
湿度敏感等级：3功能数量：1
端子数量：208字数：262144 words
字数代码：256000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：256KX18封装主体材料：PLASTIC/EPOXY
封装代码：TFBGA封装形状：SQUARE
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：225认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.45 V
最小供电电压 (Vsup)：3.15 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：15 mmBase Number Matches：1

70V7319S200BF 数据手册

 浏览型号70V7319S200BF的Datasheet PDF文件第3页浏览型号70V7319S200BF的Datasheet PDF文件第4页浏览型号70V7319S200BF的Datasheet PDF文件第5页浏览型号70V7319S200BF的Datasheet PDF文件第7页浏览型号70V7319S200BF的Datasheet PDF文件第8页浏览型号70V7319S200BF的Datasheet PDF文件第9页 
IDT70V7319S  
High-Speed 256K x 18 Synchronous Bank-Switchable Dual-Port Static RAM  
Industrial and Commercial Temperature Ranges  
Truth Table I—Read/Write and Enable Control(1,2,3,4)  
Upper Byte  
I/O9-17  
Lower Byte  
I/O0-8  
OE3  
X
X
X
X
X
X
L
CLK  
↑
CE  
1
R/W  
X
X
X
L
MODE  
Deselected–Power Down  
CE  
0
UB  
X
X
H
H
L
LB  
X
X
H
L
H
X
L
L
L
L
L
L
L
X
X
L
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Deselected–Power Down  
All Bytes Deselected  
Write to Lower Byte Only  
Write to Upper Byte Only  
Write to both Bytes  
↑
H
H
H
H
H
H
H
X
↑
DIN  
↑
H
L
L
DIN  
High-Z  
↑
L
L
DIN  
DIN  
↑
H
L
L
H
H
H
X
High-Z  
DOUT  
Read Lower Byte Only  
Read UpperByte Only  
Read both Bytes  
↑
L
H
L
DOUT  
High-Z  
↑
L
L
DOUT  
DOUT  
↑
H
X
X
X
High-Z  
High-Z  
Outputs Disabled  
5629 tbl 02  
NOTES:  
1. "H" = VIH, "L" = VIL, "X" = Don't Care.  
2. ADS, CNTEN, REPEAT are set as appropriate for address access. Refer to Truth Table II for details.  
3. OE is an asynchronous input signal.  
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.  
Truth Table II—Address and Address Counter Control(1,2,7)  
Previous  
Address  
Addr  
Used  
(3)  
ADS CNTEN REPEAT(6)  
Address  
CLK  
↑
I/O  
I/O (n) External Address Used  
I/O(n+1) Counter Enabled—Internal Address generation  
I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)  
DI/O(0) Counter Set to last valid ADS load  
MODE  
(4)  
An  
X
X
An  
An  
L
H
H
X
X
H
H
D
(5)  
An + 1  
An + 1  
An  
L
H
X
D
↑
X
An + 1  
X
H
D
↑
(4)  
X
L
↑
5629 tbl 03  
NOTES:  
1. "H" = VIH, "L" = VIL, "X" = Don't Care.  
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, UB/LB and OE.  
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.  
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and UB/LB  
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, UB/LB.  
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded  
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.  
7. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address  
FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer  
to Timing Waveform of Counter Repeat, page 18. Care should be taken during operation to avoid having both counters point to the same bank (i.e., ensure BA0L  
- BA5L ≠ BA0R - BA5R), as this condition will invalidate the access for both ports. Please refer to the functional description on page 19 for details.  
6.42  
6
1...3456789...22

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