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70V7339S166BFG8 PDF预览

70V7339S166BFG8

更新时间: 2024-02-26 01:35:14
品牌 Logo 应用领域
艾迪悌 - IDT 时钟静态存储器内存集成电路
页数 文件大小 规格书
22页 745K
描述
HIGH-SPEED 3.3V 512K x 18 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM

70V7339S166BFG8 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:CABGA
包装说明:TFBGA, BGA208,17X17,32针数:208
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.51
Samacsys Description:CHIP ARRAY BGA 15.0 X 15.0 MM X 0.8 MM P最长访问时间:12 ns
其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE最大时钟频率 (fCLK):166 MHz
I/O 类型:COMMONJESD-30 代码:S-PBGA-B208
JESD-609代码:e1长度:15 mm
内存密度:9437184 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端口数量:2
端子数量:208字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA208,17X17,32封装形状:SQUARE
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:2.5/3.3,3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.03 A最小待机电流:3.15 V
子类别:SRAMs最大压摆率:0.79 mA
最大供电电压 (Vsup):3.45 V最小供电电压 (Vsup):3.15 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:15 mm
Base Number Matches:1

70V7339S166BFG8 数据手册

 浏览型号70V7339S166BFG8的Datasheet PDF文件第2页浏览型号70V7339S166BFG8的Datasheet PDF文件第3页浏览型号70V7339S166BFG8的Datasheet PDF文件第4页浏览型号70V7339S166BFG8的Datasheet PDF文件第5页浏览型号70V7339S166BFG8的Datasheet PDF文件第6页浏览型号70V7339S166BFG8的Datasheet PDF文件第7页 
HIGH-SPEED 3.3V 512K x 18  
SYNCHRONOUS  
IDT70V7339S  
BANK-SWITCHABLE  
DUAL-PORTSTATICRAM  
WITH 3.3V OR 2.5V INTERFACE  
Š
Features:  
– 1.5ns setup to clock and 0.5ns hold on all control, data, and  
address inputs @ 200MHz  
512K x 18 Synchronous Bank-Switchable Dual-ported SRAM  
Architecture  
– Data input, address, byte enable and control registers  
– Self-timed write allows fast cycle time  
Separate byte controls for multiplexed bus and bus match-  
ingcompatibility  
64 independent 8K x 18 banks  
– 9 megabits of memory on chip  
Bank access controlled via bank address pins  
High-speed data access  
LVTTL- compatible, 3.3V (±150mV) power supply  
for core  
– Commercial:3.4ns(200MHz)/3.6ns(166MHz)/  
4.2ns(133MHz)(max.)  
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V  
(±100mV) power supply for I/Os and control signals on each  
port  
– Industrial:3.6ns(166MHz)/4.2ns(133MHz)(max.)  
Selectable Pipelined or Flow-Through output mode  
Counter enable and repeat features  
Dual chip enables allow for depth expansion without  
additionallogic  
Industrial temperature range (-40°C to +85°C) is  
available at 166MHz and 133MHz  
Available in 208-pin fine pitch Ball Grid Array (fpBGA) and  
256-pin Ball Grid Array (BGA)  
Full synchronous operation on both ports  
– 5nscycletime, 200MHzoperation(14Gbpsbandwidth)  
– Fast 3.4ns clock to data out  
Supports JTAG features compliant with IEEE 1149.1  
Green parts available, see ordering information  
FunctionalBlockDiagram  
PL/FT  
L
PL/FT  
OPT  
CLK  
ADS  
CNTEN  
REPEAT  
R/W  
R
OPT  
L
R
CLK  
ADS  
CNTEN  
L
L
L
R
R
R
REPEAT  
L
R
R/W  
CE0L  
CE1L  
L
R
MUX  
CONTROL  
LOGIC  
CONTROL  
LOGIC  
CE0R  
CE1R  
8Kx18  
MEMORY  
ARRAY  
UB  
LB  
OE  
L
L
L
UB  
LB  
OE  
R
R
R
(BANK 0)  
MUX  
MUX  
I/O  
CONTROL  
I/O  
CONTROL  
I/O0L-17L  
I/O0R-17R  
8Kx18  
MEMORY  
ARRAY  
A
12R  
0R  
(BANK 1)  
A
12L  
ADDRESS  
DECODE  
ADDRESS  
DECODE  
A
A
0L  
MUX  
BA5R  
BA4R  
BA3R  
BA2R  
BA1R  
BA0R  
BA5L  
BA4L  
BA3L  
BA2L  
BA1L  
BA0L  
BANK  
DECODE  
BANK  
DECODE  
MUX  
8Kx18  
MEMORY  
ARRAY  
(BANK 63)  
MUX  
NOTE:  
,
1. TheBank-Switchabledual-portusesatrueSRAMcore  
insteadofthetraditionaldual-portSRAMcore.Asaresult,it  
hasuniqueoperatingcharacteristics.Pleaserefertothe  
functionaldescriptiononpage18fordetails.  
5628 drw 01  
TMS  
TCK  
TRST  
TDI  
TDO  
JTAG  
AUGUST 2015  
1
DSC 5628/10  
©2015 Integrated Device Technology, Inc.  

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