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70V26L25JGI PDF预览

70V26L25JGI

更新时间: 2024-12-01 18:39:51
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
17页 143K
描述
Dual-Port SRAM, 16KX16, 35ns, CMOS, PQCC84, 1.150 X 1.150 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-84

70V26L25JGI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:LCC
包装说明:QCCN, LDCC84,1.2SQ针数:84
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.55
最长访问时间:35 nsI/O 类型:COMMON
JESD-30 代码:S-PQCC-N84JESD-609代码:e3
内存密度:262144 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:16功能数量:1
端口数量:2端子数量:84
字数:16384 words字数代码:16000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:16KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QCCN封装等效代码:LDCC84,1.2SQ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
最大待机电流:0.003 A最小待机电流:3 V
子类别:SRAMs最大压摆率:0.185 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30Base Number Matches:1

70V26L25JGI 数据手册

 浏览型号70V26L25JGI的Datasheet PDF文件第2页浏览型号70V26L25JGI的Datasheet PDF文件第3页浏览型号70V26L25JGI的Datasheet PDF文件第4页浏览型号70V26L25JGI的Datasheet PDF文件第5页浏览型号70V26L25JGI的Datasheet PDF文件第6页浏览型号70V26L25JGI的Datasheet PDF文件第7页 
IDT70V26S/L  
HIGH-SPEED 3.3V  
16K x 16 DUAL-PORT  
STATIC RAM  
Š
Features  
IDT70V26 easily expands data bus width to 32 bits or more  
using the Master/Slave select when cascading more than  
one device  
M/S = VIH for BUSY output flag on Master  
M/S = VIL for BUSY input on Slave  
On-chip port arbitration logic  
Full on-chip hardware support of semaphore signaling  
between ports  
Fully asynchronous operation from either port  
TTL-compatible, single 3.3V (±0.3V) power supply  
Available in 84-pin PGA and PLCC  
Industrial temperature range (-40°C to +85°C) is available  
for selected speeds  
True Dual-Ported memory cells which allow simultaneous  
reads of the same memory location  
High-speed access  
– Commercial:25/35/55ns (max.)  
Industrial:25ns (max.)  
Low-power operation  
IDT70V26S  
Active: 300mW (typ.)  
Standby: 3.3mW (typ.)  
IDT70V26L  
Active: 300mW (typ.)  
Standby: 660µW (typ.)  
Separate upper-byte and lower-byte control for multiplexed  
bus compatibility  
Green parts available, see ordering information  
Functional Block Diagram  
R/W  
L
R/W  
R
R
UB  
UBL  
LB  
L
LB  
CE  
OE  
R
CEL  
L
R
R
OE  
I/O8L-I/O15L  
I/O0L-I/O7L  
I/O8R-I/O15R  
I/O  
Control  
I/O  
Control  
I/O0R-I/O7R  
(1,2)  
(1,2)  
L
BUSY  
BUSY  
R
A
13L  
A
13R  
Address  
Decoder  
MEMORY  
ARRAY  
Address  
Decoder  
A
0L  
A
0R  
14  
14  
ARBITRATION  
SEMAPHORE  
LOGIC  
CEL  
CER  
SEMR  
SEM  
L
M/S  
2945 drw 01  
NOTES:  
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.  
2. BUSY outputs are non-tri-stated push-pull.  
JANUARY 2009  
1
DSC 2945/16  
©2009IntegratedDeviceTechnology,Inc.  

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