Datasheet > 70V05L20JG8

70V05L20JG8

更新时间： 2024-11-13 00:22:55

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
22页	162K
描述
HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM

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中文翻译

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数据手册

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70V05L20JG8 数据手册

IDT70V05S/L

HIGH-SPEED 3.3V

8K x 8 DUAL-PORT

STATIC RAM

Features

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

one device

M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

◆

–

Commercial: 15/20/25/35/55ns (max.)

Industrial: 20ns (max.)

◆

Low-power operation

Full on-chip hardware support of semaphore signaling

between ports

–

IDT70V05S

◆

Active:400mW(typ.)

Standby: 3.3mW (typ.)

IDT70V05L

Fully asynchronous operation from either port

TTL-compatible, single 3.3V (±0.3V) power supply

Available in 68-pin PGA and PLCC, and a 64-pin TQFP

Industrial temperature range (-40°C to +85°C) is available

for selected speeds

–

Active:380mW(typ.)

Standby: 660µW (typ.)

◆

IDT70V05 easily expands data bus width to 16 bits or more

using the Master/Slave select when cascading more than

Green parts available, see ordering information

Functional Block Diagram

OEL

OER

R/W

I/O0L- I/O7L

I/O0R-I/O7R

I/O

Control

I/O

Control

(1,2)

BUSY

12L

12R

Address

Decoder

MEMORY

ARRAY

Address

Decoder

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

M/S

(2)

INTL

INTR

2942 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

JUNE 2012

DSC 2941/10

12 3 4 5 6 7...22

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