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70T3339S200BCG PDF预览

70T3339S200BCG

更新时间: 2024-02-20 22:16:16
品牌 Logo 应用领域
艾迪悌 - IDT 时钟PC静态存储器内存集成电路
页数 文件大小 规格书
27页 829K
描述
HIGH-SPEED SYNCHRONOUS DUAL-PORT STATIC RAM

70T3339S200BCG 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:CABGA
包装说明:LBGA, BGA256,16X16,40针数:256
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.23
Samacsys Confidence:3Samacsys Status:Released
Samacsys PartID:11322550Samacsys Pin Count:256
Samacsys Part Category:Integrated CircuitSamacsys Package Category:BGA
Samacsys Footprint Name:BC256-_Samacsys Released Date:2020-02-14 13:40:57
Is Samacsys:N最长访问时间:3.4 ns
其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE最大时钟频率 (fCLK):200 MHz
I/O 类型:COMMONJESD-30 代码:S-CBGA-B256
JESD-609代码:e1长度:17 mm
内存密度:9437184 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端口数量:2
端子数量:256字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:512KX18输出特性:3-STATE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:LBGA
封装等效代码:BGA256,16X16,40封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:2.5,2.5/3.3 V
认证状态:Not Qualified座面最大高度:1.7 mm
最大待机电流:0.015 A最小待机电流:2.4 V
子类别:SRAMs最大压摆率:0.525 mA
最大供电电压 (Vsup):2.6 V最小供电电压 (Vsup):2.4 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Silver/Copper (Sn/Ag/Cu)端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:17 mm
Base Number Matches:1

70T3339S200BCG 数据手册

 浏览型号70T3339S200BCG的Datasheet PDF文件第2页浏览型号70T3339S200BCG的Datasheet PDF文件第3页浏览型号70T3339S200BCG的Datasheet PDF文件第4页浏览型号70T3339S200BCG的Datasheet PDF文件第5页浏览型号70T3339S200BCG的Datasheet PDF文件第6页浏览型号70T3339S200BCG的Datasheet PDF文件第7页 
HIGH-SPEED 2.5V  
512/256/128K X 18  
SYNCHRONOUS  
IDT70T3339/19/99S  
DUAL-PORT STATIC RAM  
Š
WITH 3.3V OR 2.5V INTERFACE  
Features:  
– 1.5ns setup to clock and 0.5ns hold on all control, data,  
and address inputs @ 200MHz  
True Dual-Port memory cells which allow simultaneous  
access of the same memory location  
High-speed data access  
– Self-timedwriteallowsfastcycletime  
Separate byte controls for multiplexed bus and bus  
matching compatibility  
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/  
4.2ns (133MHz)(max.)  
Dual Cycle Deselect (DCD) for Pipelined Output Mode  
2.5V (±100mV) power supply for core  
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)  
Selectable Pipelined or Flow-Through output mode  
Counter enable and repeat features  
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V  
(±100mV) power supply for I/Os and control signals on  
each port  
Dual chip enables allow for depth expansion without  
additional logic  
Industrial temperature range (-40°C to +85°C) is  
available at 166MHz and 133MHz  
Interrupt and Collision Detection Flags  
Full synchronous operation on both ports  
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)  
– Fast 3.4ns clock to data out  
Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine  
pitch Ball Grid Array (fpBGA)  
Supports JTAG features compliant with IEEE 1149.1  
Green parts available, see ordering information  
– Data input, address, byte enable and control registers  
FunctionalBlockDiagram  
UBL  
UBR  
LBL  
LBR  
FT/PIPE  
L
0a 1a  
a
0b 1b  
b
1b 0b  
b
1a 0a  
a
FT/PIPER  
1/0  
1/0  
R/WL  
R/W  
R
CE0L  
CE0R  
1
1
CE1R  
CE1L  
B
W
0
B
W
1
B B  
0
0
W W  
1
0
R
L
L
R
1/0  
1/0  
Dout0-8_L  
Dout9-17_L  
Dout0-8_R  
Dout9-17_R  
OE  
L
OE  
R
,
0a 1a  
1b 0b 1a 0a  
ab  
0b  
1b  
0/1  
FT/PIPE  
L
0/1  
FT/PIPER  
ba  
512/256/128K x 18  
MEMORY  
ARRAY  
Din_L  
I/O0R - I/O17R  
I/O0L - I/O17L  
Din_R  
,
CLK  
R
CLK  
L
(1)  
18R  
(1)  
18L  
A
A
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
A
0L  
REPEAT  
ADS  
CNTEN  
A
0R  
REPEAT  
ADS  
CNTEN  
ADDR_R  
ADDR_L  
L
R
R
L
R
L
TDI  
TCK  
TMS  
TRST  
INTERRUPT  
CE  
CE1  
0
R
R
CE  
0
JTAG  
L
COLLISION  
DETECTION  
LOGIC  
TDO  
CE1  
L
R/W  
R
R/  
W
L
COL L  
COL  
R
INT  
L
INTR  
5652 drw 01  
(2)  
(2)  
ZZR  
ZZ  
ZZ  
L
CONTROL  
LOGIC  
NOTES:  
1. Address A18 is a NC for the IDT70T3319. Also, Addresses A18 and A17 are NC's for the IDT70T3399.  
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and  
OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.  
JUNE 2015  
1
DSC-5652/8  
©2015 Integrated Device Technology, Inc.  

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