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70P244L40BYI PDF预览

70P244L40BYI

更新时间: 2024-01-28 00:52:27
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
14页 111K
描述
Application Specific SRAM, 4KX16, 40ns, CMOS, PBGA81, 0.50 MM PITCH, BGA-81

70P244L40BYI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active包装说明:BGA, BGA81,9X9,20
Reach Compliance Code:not_compliant风险等级:5.71
最长访问时间:40 nsI/O 类型:COMMON
JESD-30 代码:S-PBGA-B81JESD-609代码:e0
内存密度:65536 bit内存集成电路类型:APPLICATION SPECIFIC SRAM
内存宽度:16功能数量:1
端口数量:2端子数量:81
字数:4096 words字数代码:4000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:4KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA81,9X9,20
封装形状:SQUARE封装形式:GRID ARRAY
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:1.8 V认证状态:Not Qualified
最大待机电流:0.000006 A子类别:SRAMs
最大压摆率:0.04 mA最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:BALL端子节距:0.5 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
Base Number Matches:1

70P244L40BYI 数据手册

 浏览型号70P244L40BYI的Datasheet PDF文件第8页浏览型号70P244L40BYI的Datasheet PDF文件第9页浏览型号70P244L40BYI的Datasheet PDF文件第10页浏览型号70P244L40BYI的Datasheet PDF文件第11页浏览型号70P244L40BYI的Datasheet PDF文件第12页浏览型号70P244L40BYI的Datasheet PDF文件第14页 
IDT70P264/254/244L  
Low Power 1.8V 16K/8K/4K x 16 Dual-Port Static RAM  
Datasheet  
Industrial Temperature Range  
Truth Table II — Interrupt Flag(1)  
Left Port  
Right Port  
(1)  
(1)  
R/W  
L
L
A
13L-A0L  
R/W  
R
A
13R-A0R  
Function  
Set Right INT Flag  
Reset Right INT Flag  
Set Left INT Flag  
Reset Left INT Flag  
CE  
L
OE  
L
INT  
X
L
CE  
R
OE  
R
INTR  
L
X
X
L
X
X
X
L
3FFF  
X
X
X
L
L
X
X
L
X
3FFF  
3FFE  
X
L
R
X
X
X
H
X
X
R
X
X
L
L
X
X
L
X
3FFE  
H
X
L
7148 tbl 14  
NOTES:  
1. A13X is a NC for IDT70P254. A13X and A12X are NC for IDT70P244. Interrupt Addresses are 1FFF and 1FFE for IDT70P254 and FFF and FFE for IDT70P244.  
Interrupts  
FunctionalDescription  
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox  
ormessagecenter)is assignedtoeachport. Theleftportinterruptflag  
(INTL) is asserted when the right port writes to memory location 3FFE  
(HEX) (1FFE for IDT70P254, FFE for IDT70P244), where a write is  
defined as the CE=R/W=VIL per Truth Table II. The left port clears the  
interruptbyaccessingaddresslocation3FFE (1FFEforIDT70P254,FFE  
forIDT70P244)whenCER=OER=VIL,R/Wisa"don'tcare".Likewise,  
therightportinterruptflag(INTR)isassertedwhentheleftportwritesto  
memorylocation3FFF(HEX)(1FFFforIDT70P254,FFFforIDT70P244)  
andtocleartheinterruptflag(INTR),therightportmustreadthememory  
location3FFF.Themessage(16bits)at3FFEor3FFFisuser-defined,  
sinceitisanaddressableSRAMlocation.Iftheinterruptfunctionisnotused,  
addresslocations3FFEand3FFFarenotusedasmailboxes,butaspart  
of the random access memory. Refer to Truth Table II for the interrupt  
operation.  
The IDT70P264/254/244provides twoports withseparate control,  
address andI/Opins thatpermitindependentaccess toanylocationin  
memory.TheIDT70P264/254/244hasanautomaticpowerdownfeature  
controlled by CE. The CE controls on-chip power down circuitry that  
permitstherespectiveporttogointoastandbymodewhennotselected  
(CE HIGH).Whenaportis enabled,access totheentirememoryarray  
ispermitted.  
PowerSupply  
Each port can operate on independent I/O voltages. This is deter-  
minedbywhatis connectedtotheVDDIOL andVDDpins. Thesupported  
I/O standards are 1.8V/2.5V LVCMOS and 3.0V LVTTL.  
TheIDT70P264/254/244includespowersupplyisolationfunctional-  
ity which aids system power management. VDD and VDDIOL can be  
independentlypoweredup/downwhichallowstheleft portortherightport  
andcoretobepowereddownwhennotinuse. IfVDDIOL ispowereddown,  
butVDD remainspoweredupallinputstothecorefromtheleftportwillbe  
forcedtodeassertedstatesatfullswingDCvaluestominimizeleakage  
currentandactivepowerconsumption. IfVDDispowereddownbutVDDIOL  
remainpoweredup,alloutputsfortheleftport willremaininthestatethey  
were in prior to power down.  
TheinterruptoutputsoftheIDT70P264/254/244shouldbeconnected  
to an interrupt power supply (VDDINTX) through an external pull-up  
resistor. AslongasVDDINTR >VDDandVDDINTL>VDDQL,therewill  
be no current flowing between VDDINTx and VDD/VDDQL.  
6.42  
13  

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