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709359L6PFG8 PDF预览

709359L6PFG8

更新时间: 2024-10-29 00:52:11
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
15页 685K
描述
HIGH-SPEED 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

709359L6PFG8 技术参数

生命周期:Obsolete包装说明:QFP,
Reach Compliance Code:compliant风险等级:5.84
最长访问时间:6.5 ns其他特性:FLOW-THROUGH
JESD-30 代码:X-PQFP-G100内存密度:147456 bit
内存集成电路类型:DUAL-PORT SRAM内存宽度:18
功能数量:1端子数量:100
字数:8192 words字数代码:8000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:8KX18
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装形状:UNSPECIFIED封装形式:FLATPACK
并行/串行:PARALLEL最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子位置:QUADBase Number Matches:1

709359L6PFG8 数据手册

 浏览型号709359L6PFG8的Datasheet PDF文件第2页浏览型号709359L6PFG8的Datasheet PDF文件第3页浏览型号709359L6PFG8的Datasheet PDF文件第4页浏览型号709359L6PFG8的Datasheet PDF文件第5页浏览型号709359L6PFG8的Datasheet PDF文件第6页浏览型号709359L6PFG8的Datasheet PDF文件第7页 
HIGH-SPEED 8/4K x 18  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
IDT709359/49L  
Features  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:6.5/7.5/9ns(max.)  
– Industrial: 7.5ns (max.)  
Full synchronous operation on both ports  
– 3.5ns setup to clock and 0ns hold on all control, data, and  
address inputs  
– Data input, address, and control registers  
– Fast 6.5ns clock to data out in the Pipelined output mode  
– Self-timed write allows fast cycle time  
Low-power operation  
– IDT709359/49L  
– 10ns cycle time, 100MHz operation in Pipelined output mode  
Separate upper-byte and lower-byte controls for  
multiplexed bus and bus matching compatibility  
TTL- compatible, single 5V (±10%) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for 83 MHz  
Active:925mW(typ.)  
Standby: 2.5mW (typ.)  
Flow-Through or Pipelined output mode on either Port via  
the FT/PIPE pins  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Available in a 100-pin Thin Quad Flatpack (TQFP) package  
Green parts available, see ordering informaiton  
Functional Block Diagram  
R/  
WL  
R/  
W
R
R
UB  
L
UB  
CE0L  
CE1L  
CE0R  
CE1R  
1
0
1
0
0/1  
0/1  
LB  
L
LB  
OE  
R
R
OEL  
1b 0b  
0a 1a  
1a 0a  
a
0b 1b  
b
FT/PIPE  
L
0/1  
0/1  
b
a
FT/PIPE  
R
I/O9L-I/O17L  
I/O0L-I/O8L  
I/O9R-I/O17R  
I/O0R-I/O8R  
(1)  
I/O  
Control  
I/O  
Control  
(1)  
12L  
A
A12R  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A
C0LRK  
R
R
A
0L  
CLK  
L
L
ADS  
CNTEN  
ADS  
CNTEN  
R
L
CNTRST  
L
CNTRST  
R
5633 drw 01  
NOTE:  
1. A12 is a NC for IDT709349.  
MAY 2015  
1
DSC-5633/4  
©2015 Integrated Device Technology, Inc.  

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