Datasheet > 709369L12PFGI8

709369L12PFGI8

更新时间： 2024-10-29 00:54:31

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	210K
描述
HIGH-SPEED 32/16K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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中文翻译

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数据手册

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709369L12PFGI8 数据手册

HIGH-SPEED 32/16K x 18

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

IDT709379/69L

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features

True Dual-Ported memory cells which allow simultaneous

◆

Full synchronous operation on both ports

– 4ns setup to clock and 0ns hold on all control, data, and

address inputs

– Data input, address, and control registers

– Fast 7.5ns clock to data out in the Pipelined output mode

– Self-timed write allows fast cycle time

– 10ns cycle time, 100MHz operation in Pipelined output mode

Separate upper-byte and lower-byte controls for

multiplexed bus and bus matching compatibility

TTL- compatible, single 5V ( 10%) power supply

Industrial temperature range (–40°C to +85°C) is

available for selected speeds

access of the same memory location

High-speed clock to data access

– Commercial:7.5/9/12ns(max.)

– Insustrial:9ns(max.)

Low-power operation

– IDT709379/69L

◆

Active: 1.2W (typ.)

Standby: 2.5mW (typ.)

Flow-Through or Pipelined output mode on either Port via

the FT/PIPE pins

Counter enable and reset features

Dual chip enables allow for depth expansion without

additional logic

◆

Available in a 100-pin Thin Quad Flatpack (TQFP) package

Green parts available, see ordering information

Functional Block Diagram

R/W

CE0L

CE1L

CE0R

CE1R

0/1

1b 0b

0a 1a

1a 0a

0b 1b

FT/PIPE

0/1

FT/PIPER

I/O9L-I/O17L

I/O0L-I/O8L

I/O9R-I/O17R

I/O0R-I/O8R

I/O

Control

I/O

Control

14L⁽¹⁾

14R⁽¹⁾

Counter/

Address

Reg.

Counter/

Address

Reg.

MEMORY

ARRAY

CLK

ADS

CLK

ADS

CNTEN

CNTRST

4845 drw 01

NOTE:

1. A14X is a NC for IDT709369.

FEBRUARY 2018

DSC-4845/8

12 3 4 5 6 7...16

中文翻译

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