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709289L12PFGI8 PDF预览

709289L12PFGI8

更新时间: 2024-10-29 01:23:27
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
16页 701K
描述
HIGH-SPEED 64K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

709289L12PFGI8 数据手册

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HIGH-SPEED 64K x 16  
IDT709289L  
SYNCHRONOUS PIPELINED  
DUAL-PORT STATIC RAM  
Features  
True Dual-Ported memory cells which allow simultaneous  
access of the same memory location  
High-speed clock to data access  
– Commercial:7.5/9/12ns(max.)  
– Industrial: 9ns (max.)  
Full synchronous operation on both ports  
– 4ns setup to clock and 0ns hold on all control, data, and  
address inputs  
– Data input, address, and control registers  
– Fast 7.5ns clock to data out in the Pipelined output mode  
– Self-timed write allows fast cycle time  
Low-power operation  
– IDT709289L  
– 12ns cycle time, 83MHz operation in Pipelined output mode  
Separate upper-byte and lower-byte controls for  
multiplexed bus and bus matching compatibility  
TTL- compatible, single 5V (±10%) power supply  
Industrial temperature range (–40°C to +85°C) is  
available for selected speeds  
Active: 1.2W (typ.)  
Standby: 2.5mW (typ.)  
Flow-Through or Pipelined output mode on either Port via  
the FT/PIPE pins  
Counter enable and reset features  
Dual chip enables allow for depth expansion without  
additional logic  
Available in a 100-pin Thin Quad Flatpack (TQFP) package  
Green parts available, see ordering information  
Functional Block Diagram  
R/  
WL  
R/  
W
R
R
UB  
L
UB  
CE0L  
CE1L  
CE0R  
CE1R  
1
0
1
0
0/1  
0/1  
LB  
L
LB  
OE  
R
R
OEL  
1b 0b  
0a 1a  
1a 0a  
a
0b 1b  
b
FT/PIPE  
L
0/1  
0/1  
b
a
FT/PIPE  
R
I/O8L-I/O15L  
I/O0L-I/O7L  
I/O8R-I/O15R  
I/O0R-I/O7R  
I/O  
Control  
I/O  
Control  
A
15R  
A
15L  
Counter/  
Address  
Reg.  
Counter/  
Address  
Reg.  
MEMORY  
ARRAY  
A
C0LRK  
R
R
A
0L  
L
L
L
CLK  
ADS  
ADS  
CNTEN  
R
CNTEN  
CNTRST  
L
CNTRST  
R
4842 drw 01  
FEBRUARY 2015  
1
DSC-4842/7  
©2015 Integrated Device Technology, Inc.  

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