Datasheet > 709279S7G

709279S7G

更新时间： 2024-10-29 05:44:07

品牌	Logo	应用领域
艾迪悌 - IDT		静态存储器
页数	文件大小	规格书
18页	192K
描述
Dual-Port SRAM, 32KX16, 18ns, CMOS, CPGA108, PGA-108

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中文翻译

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数据手册

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709279S7G 数据手册

HIGH-SPEED 32/16K x 16

SYNCHRONOUS

IDT709279/69S/L

DUAL-PORT STATIC RAM

Features

◆

True Dual-Ported memory cells which allow simultaneous

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 4ns setup to clock and 1ns hold on all control, data, and

addressinputs

access of the same memory location

High-speed clock to data access

◆

– Commercial:6.5/7.5/9/12/15ns(max.)

– Industrial:12ns (max.)

Low-power operation

◆

– Data input, address, and control registers

– IDT709279/69S

Active:950mW(typ.)

Standby: 5mW (typ.)

– IDT709279/69L

Active:950mW(typ.)

Standby: 1mW (typ.)

Flow-Through or Pipelined output mode on either port via

the FT/PIPE pin

Counter enable and reset features

– Fast 6.5ns clock to data out in the Pipelined output mode

– Self-timedwriteallowsfastcycletime

– 10ns cycle time, 100MHz operation in Pipelined output mode

Separate upper-byte and lower-byte controls for

multiplexed bus and bus matching compatibility

TTL- compatible, single 5V (±10%) power supply

Industrial temperature range (–40°C to +85°C) is

available for selected speeds

◆

Available in a 100-pin Thin Quad Flatpack (TQFP) package

FunctionalBlockDiagram

R/W

UBR

UBL

CE0L

CE1L

CE0R

CE1R

0/1

1a 0a

1b 0b

0a 1a

0b 1b

FT/PIPE

0/1

FT/PIPE

I/O8L

I/O15L

I/O8R-I/O15R

I/O

Control

I/O

Control

I/O0L-I/O7L

I/O0R-I/O7R

(1)

14R

14L

Counter/

Address

Reg.

Counter/

Address

Reg.

MEMORY

ARRAY

CLK

ADS

CNTEN

CLK

ADS

CNTEN

CNTRST

3243 drw 01

NOTE:

1. A^14Xis a NC for IDT709269.

JANUARY 2009

DSC-3243/14

12 3 4 5 6 7...18

中文翻译

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