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7052S20GG PDF预览

7052S20GG

更新时间: 2024-10-29 00:43:07
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
12页 712K
描述
HIGH-SPEED 2K x 8 FourPort STATIC RAM

7052S20GG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:PGA
包装说明:PGA, PGA108,12X12针数:108
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.1
最长访问时间:20 nsI/O 类型:COMMON
JESD-30 代码:S-CPGA-P108JESD-609代码:e3
长度:30.48 mm内存密度:16384 bit
内存集成电路类型:FOUR-PORT SRAM内存宽度:8
功能数量:1端口数量:4
端子数量:108字数:2048 words
字数代码:2000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:2KX8输出特性:3-STATE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:PGA
封装等效代码:PGA108,12X12封装形状:SQUARE
封装形式:GRID ARRAY并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:5.207 mm
最大待机电流:0.015 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.3 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:PIN/PEG
端子节距:2.54 mm端子位置:PERPENDICULAR
处于峰值回流温度下的最长时间:30宽度:30.48 mm
Base Number Matches:1

7052S20GG 数据手册

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IDT7052S/L  
HIGH-SPEED  
2K x 8 FourPortTM  
STATIC RAM  
Features  
Battery backup operation—2V data retention  
High-speed access  
TTL-compatible; single 5V (±10%) power supply  
– Commercial:20/25/35ns(max.)  
– Industrial: 25ns (max.)  
Available in 120 pin Thin Quad Flatpacks and 108 pin PGA  
Military product compliant to MIL-PRF-38535 QML  
Industrial temperature range (–40°C to +85°C) is available  
for selected speeds  
– Military:25/35ns(max.)  
Low-power operation  
– IDT7052S  
Green parts available, see ordering information  
Active:750mW(typ.)  
Standby: 7.5mW (typ.)  
– IDT7052L  
Description  
Active:750mW(typ.)  
Standby: 1.5mW (typ.)  
TheIDT7052isahigh-speed2Kx8FourPortStaticRAMdesigned  
to be used in systems where multiple access into a common RAM is  
required.ThisFourPortStaticRAMoffersincreasedsystemperformance  
inmultiprocessorsystemsthathaveaneedtocommunicateinrealtimeand  
alsooffersaddedbenefitforhigh-speedsystemsinwhichmultipleaccess  
is required in the same cycle.  
True FourPort memory cells which allow simultaneous  
access of the same memory locations  
Fully asynchronous operation from each of the four ports:  
P1, P2, P3, P4  
Versatile control for write-inhibit: separate BUSY input to  
TheIDT7052isalsodesignedtobeusedinsystemswhereon-chip  
hardware port arbitration is not needed. This part lends itself to those  
control write-inhibit for each of the four ports  
FunctionalBlockDiagram  
R/WP1  
CEP1  
R/WP4  
CEP4  
OEP1  
OEP4  
COLUMN  
I/O  
COLUMN  
I/O0P1-I/O7P1  
BUSYP1  
I/O0P4-I/O7P4  
I/O  
BUSYP4  
PORT 1  
PORT 4  
ADDRESS  
DECODE  
LOGIC  
ADDRESS  
DECODE  
LOGIC  
A0P1 - A10P1  
A0P4 - A10P4  
MEMORY  
ARRAY  
PORT 2  
ADDRESS  
DECODE  
LOGIC  
PORT 3  
ADDRESS  
DECODE  
LOGIC  
A0P2 - A10P2  
A0P3 - A10P3  
BUSYP2  
BUSYP3  
COLUMN  
I/O  
COLUMN  
I/O  
I/O0P2-I/O7P2  
I/O0P3-I/O7P3  
OEP2  
OEP3  
CEP2  
CEP3  
R/WP3  
R/WP2  
2674 drw 01  
JULY 2016  
1
DSC 2674/15  
©2016 Integrated Device Technology, Inc.  

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