Datasheet > 7028L15PFGI

7028L15PFGI

更新时间： 2024-10-30 00:58:15

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
18页	179K
描述
HIGH-SPEED 64K x 16 DUAL-PORT STATIC RAM

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中文翻译

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数据手册

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7028L15PFGI 数据手册

HIGH-SPEED

64K x 16 DUAL-PORT

STATIC RAM

IDT7028L

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features

True Dual-Ported memory cells which allow simultaneous

◆

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate upper-byte and lower-byte controls for multi-

plexed bus and bus matching compatibility

TTL-compatible, single 5V ( 10%) power supply

Available in a 100-pin TQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

reads of the same memory location

High-speed access

◆

– Commercial: 15/20ns (max.)

– Industrial: 20ns (max.)

Low-power operation

◆

– IDT7028L

Active: 1W (typ.)

Standby: 1mW (typ.)

Dual chip enables allow for depth expansion without

◆

external logic

IDT7028 easily expands data bus width to 32 bits or

◆

more using the Master/Slave select when cascading more

than one device

◆

Functional Block Diagram

R/W

CE0L

CE0R

CE1L

CE1R

LBR

I/O^8-15L

I/O8-15R

I/O0-7R

I/O

Control

I/O

Control

0-7L

I/O

(1,2)

BUSY

64Kx16

MEMORY

ARRAY

7028

15L

15R

Address

Decoder

Address

Decoder

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE0R

CE0L

CE1L

OEL

CE1R

OER

R/W

R/WR

SEM

(2)

INTR

INT

M/S⁽²⁾

NOTES:

1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH).

2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

4836 drw 01

JUNE 2018

DSC-4836/5

12 3 4 5 6 7...18

中文翻译

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